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Message-ID: <CA+55aFyFLzH71Tke858x0cjCiRO48vc1W9oVmVkO43rtjezqOg@mail.gmail.com>
Date: Tue, 17 Jul 2018 09:19:15 -0700
From: Linus Torvalds <torvalds@...ux-foundation.org>
To: Michael Ellerman <mpe@...erman.id.au>
Cc: Peter Zijlstra <peterz@...radead.org>,
Paul McKenney <paulmck@...ux.vnet.ibm.com>,
Alan Stern <stern@...land.harvard.edu>,
andrea.parri@...rulasolutions.com,
Will Deacon <will.deacon@....com>,
Akira Yokosawa <akiyks@...il.com>,
Boqun Feng <boqun.feng@...il.com>,
Daniel Lustig <dlustig@...dia.com>,
David Howells <dhowells@...hat.com>,
Jade Alglave <j.alglave@....ac.uk>,
Luc Maranget <luc.maranget@...ia.fr>,
Nick Piggin <npiggin@...il.com>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2] tools/memory-model: Add extra ordering for locks and
remove it for ordinary release/acquire
On Tue, Jul 17, 2018 at 7:45 AM Michael Ellerman <mpe@...erman.id.au> wrote:
>
>
> Interesting. I don't see anything as high as 18%, it's more spread out:
>
> 7.81% context_switch [kernel.kallsyms] [k] cgroup_rstat_updated
Oh, see that's the difference.
You're running in a non-root cgroup, I think.
That also means that your scheduler overhead has way more spinlocks,
and in particular, you have that
raw_spinlock_t *cpu_lock = per_cpu_ptr(&cgroup_rstat_cpu_lock, cpu);
..
raw_spin_lock_irqsave(cpu_lock, flags);
there too.
So you have at least twice the spinlocks that my case had, and yes,
the costs are way more spread out because your case has all that
cgroup accounting too.
That said, I don't understand the powerpc memory ordering. I thought
the rules were "isync on lock, lwsync on unlock".
That's what the AIX docs imply, at least.
In particular, I find:
"isync is not a memory barrier instruction, but the
load-compare-conditional branch-isync sequence can provide this
ordering property"
so why are you doing "sync/lwsync", when it sounds like "isync/lwsync"
(for lock/unlock) is the right thing and would already give memory
barrier semantics?
Linus
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