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Message-ID: <alpine.DEB.2.21.1807200837380.1693@nanos.tec.linutronix.de>
Date:   Fri, 20 Jul 2018 08:38:19 +0200 (CEST)
From:   Thomas Gleixner <tglx@...utronix.de>
To:     David Wang <davidwang@...oxin.com>
cc:     rjw@...ysocki.net, mingo@...hat.com, len.brown@...el.com,
        pavel@....cz, "H. Peter Anvin" <hpa@...or.com>, x86@...nel.org,
        linux-pm@...nel.org, LKML <linux-kernel@...r.kernel.org>,
        brucechang@...-alliance.com, cooperyan@...oxin.com,
        qiyuanwang@...oxin.com, benjaminpan@...tech.com,
        lukelin@...cpu.com, timguo@...oxin.com,
        "Rafael J. Wysocki" <rafael.j.wysocki@...el.com>
Subject: Re: [PATCH v3] Optimize C3 entry on Centaur CPUs

On Tue, 29 May 2018, David Wang wrote:

> For new Centaur CPUs the ucode will take care of the preservation of cache coherence
> between CPU cores in C-states regardless of how deep the C-states are. So, it is not
> necessary to flush the caches in software befor entering C3.
> 
> Signed-off-by: David Wang <davidwang@...oxin.com>

Reviewed-by: Thomas Gleixner <tglx@...utronix.de>

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