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Message-ID: <5e51036b-a0b0-9cb4-4698-cf830309ef8a@nvidia.com>
Date: Fri, 20 Jul 2018 09:12:26 +0100
From: Jon Hunter <jonathanh@...dia.com>
To: Marcel Ziswiler <marcel@...wiler.com>,
<devicetree@...r.kernel.org>, <linux-tegra@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
CC: Marcel Ziswiler <marcel.ziswiler@...adex.com>,
Thierry Reding <thierry.reding@...il.com>,
Linus Walleij <linus.walleij@...aro.org>,
<linux-gpio@...r.kernel.org>, Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>
Subject: Re: [PATCH] pinctrl: tegra: fix spelling in devicetree binding
document
On 20/07/18 08:52, Marcel Ziswiler wrote:
> From: Marcel Ziswiler <marcel.ziswiler@...adex.com>
>
> This fixes a spelling mistake.
>
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@...adex.com>
>
> ---
>
> Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt
> index ecb5c0d25218..f4d06bb0b55a 100644
> --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt
> @@ -17,7 +17,7 @@ Tegra124 adds the following optional properties for pin configuration subnodes.
> The macros for options are defined in the
> include/dt-binding/pinctrl/pinctrl-tegra.h.
> - nvidia,enable-input: Integer. Enable the pin's input path.
> - enable :TEGRA_PIN_ENABLE0 and
> + enable :TEGRA_PIN_ENABLE and
> disable or output only: TEGRA_PIN_DISABLE.
> - nvidia,open-drain: Integer.
> enable: TEGRA_PIN_ENABLE.
Thanks for fixing! Can you also fix up the one in nvidia,tegra210-pinmux.txt as well?
Cheers!
Jon
--
nvpublic
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