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Message-ID: <20180721085503.67a8a800@bbrezillon>
Date: Sat, 21 Jul 2018 08:55:03 +0200
From: Boris Brezillon <boris.brezillon@...tlin.com>
To: Miquel Raynal <miquel.raynal@...tlin.com>
Cc: Wenyou Yang <wenyou.yang@...rochip.com>,
Josh Wu <rainyfeeling@...look.com>,
Tudor Ambarus <Tudor.Ambarus@...rochip.com>,
Richard Weinberger <richard@....at>,
David Woodhouse <dwmw2@...radead.org>,
Brian Norris <computersforpeace@...il.com>,
Marek Vasut <marek.vasut@...il.com>,
Nicolas Ferre <nicolas.ferre@...rochip.com>,
Alexandre Belloni <alexandre.belloni@...tlin.com>,
Kamal Dasu <kdasu.kdev@...il.com>,
Masahiro Yamada <yamada.masahiro@...ionext.com>,
Han Xu <han.xu@....com>,
Harvey Hunt <harveyhuntnexus@...il.com>,
Vladimir Zapolskiy <vz@...ia.com>,
Sylvain Lemieux <slemieux.tyco@...il.com>,
Xiaolei Li <xiaolei.li@...iatek.com>,
Matthias Brugger <matthias.bgg@...il.com>,
Maxime Ripard <maxime.ripard@...tlin.com>,
Chen-Yu Tsai <wens@...e.org>,
Marc Gonzalez <marc.w.gonzalez@...e.fr>,
Mans Rullgard <mans@...sr.com>, Stefan Agner <stefan@...er.ch>,
linux-mtd@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
bcm-kernel-feedback-list@...adcom.com,
linux-mediatek@...ts.infradead.org
Subject: Re: [PATCH v4 07/35] mtd: rawnand: fsmc: convert driver to
nand_scan()
On Fri, 20 Jul 2018 17:14:59 +0200
Miquel Raynal <miquel.raynal@...tlin.com> wrote:
> Two helpers have been added to the core to make ECC-related
> configuration between the detection phase and the final NAND scan. Use
> these hooks and convert the driver to just use nand_scan() instead of
> both nand_scan_ident() and nand_scan_tail().
>
> Signed-off-by: Miquel Raynal <miquel.raynal@...tlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@...tlin.com>
> ---
> drivers/mtd/nand/raw/fsmc_nand.c | 148 +++++++++++++++++++++------------------
> 1 file changed, 78 insertions(+), 70 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/fsmc_nand.c b/drivers/mtd/nand/raw/fsmc_nand.c
> index 59524d181bfe..f418236fa020 100644
> --- a/drivers/mtd/nand/raw/fsmc_nand.c
> +++ b/drivers/mtd/nand/raw/fsmc_nand.c
> @@ -919,6 +919,82 @@ static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
> return 0;
> }
>
> +static int fsmc_nand_attach_chip(struct nand_chip *nand)
> +{
> + struct mtd_info *mtd = nand_to_mtd(nand);
> + struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
> +
> + if (AMBA_REV_BITS(host->pid) >= 8) {
> + switch (mtd->oobsize) {
> + case 16:
> + case 64:
> + case 128:
> + case 224:
> + case 256:
> + break;
> + default:
> + dev_warn(host->dev,
> + "No oob scheme defined for oobsize %d\n",
> + mtd->oobsize);
> + return -EINVAL;
> + }
> +
> + mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops);
> +
> + return 0;
> + }
> +
> + switch (nand->ecc.mode) {
> + case NAND_ECC_HW:
> + dev_info(host->dev, "Using 1-bit HW ECC scheme\n");
> + nand->ecc.calculate = fsmc_read_hwecc_ecc1;
> + nand->ecc.correct = nand_correct_data;
> + nand->ecc.bytes = 3;
> + nand->ecc.strength = 1;
> + break;
> +
> + case NAND_ECC_SOFT:
> + if (nand->ecc.algo == NAND_ECC_BCH) {
> + dev_info(host->dev,
> + "Using 4-bit SW BCH ECC scheme\n");
> + break;
> + }
> +
> + case NAND_ECC_ON_DIE:
> + break;
> +
> + default:
> + dev_err(host->dev, "Unsupported ECC mode!\n");
> + return -ENOTSUPP;
> + }
> +
> + /*
> + * Don't set layout for BCH4 SW ECC. This will be
> + * generated later in nand_bch_init() later.
> + */
> + if (nand->ecc.mode == NAND_ECC_HW) {
> + switch (mtd->oobsize) {
> + case 16:
> + case 64:
> + case 128:
> + mtd_set_ooblayout(mtd,
> + &fsmc_ecc1_ooblayout_ops);
> + break;
> + default:
> + dev_warn(host->dev,
> + "No oob scheme defined for oobsize %d\n",
> + mtd->oobsize);
> + return -EINVAL;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static const struct nand_controller_ops fsmc_nand_controller_ops = {
> + .attach_chip = fsmc_nand_attach_chip,
> +};
> +
> /*
> * fsmc_nand_probe - Probe function
> * @pdev: platform device structure
> @@ -1048,76 +1124,8 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
> /*
> * Scan to find existence of the device
> */
> - ret = nand_scan_ident(mtd, 1, NULL);
> - if (ret) {
> - dev_err(&pdev->dev, "No NAND Device found!\n");
> - goto release_dma_write_chan;
> - }
> -
> - if (AMBA_REV_BITS(host->pid) >= 8) {
> - switch (mtd->oobsize) {
> - case 16:
> - case 64:
> - case 128:
> - case 224:
> - case 256:
> - break;
> - default:
> - dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n",
> - mtd->oobsize);
> - ret = -EINVAL;
> - goto release_dma_write_chan;
> - }
> -
> - mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops);
> - } else {
> - switch (nand->ecc.mode) {
> - case NAND_ECC_HW:
> - dev_info(&pdev->dev, "Using 1-bit HW ECC scheme\n");
> - nand->ecc.calculate = fsmc_read_hwecc_ecc1;
> - nand->ecc.correct = nand_correct_data;
> - nand->ecc.bytes = 3;
> - nand->ecc.strength = 1;
> - break;
> -
> - case NAND_ECC_SOFT:
> - if (nand->ecc.algo == NAND_ECC_BCH) {
> - dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
> - break;
> - }
> -
> - case NAND_ECC_ON_DIE:
> - break;
> -
> - default:
> - dev_err(&pdev->dev, "Unsupported ECC mode!\n");
> - goto release_dma_write_chan;
> - }
> -
> - /*
> - * Don't set layout for BCH4 SW ECC. This will be
> - * generated later in nand_bch_init() later.
> - */
> - if (nand->ecc.mode == NAND_ECC_HW) {
> - switch (mtd->oobsize) {
> - case 16:
> - case 64:
> - case 128:
> - mtd_set_ooblayout(mtd,
> - &fsmc_ecc1_ooblayout_ops);
> - break;
> - default:
> - dev_warn(&pdev->dev,
> - "No oob scheme defined for oobsize %d\n",
> - mtd->oobsize);
> - ret = -EINVAL;
> - goto release_dma_write_chan;
> - }
> - }
> - }
> -
> - /* Second stage of scan to fill MTD data-structures */
> - ret = nand_scan_tail(mtd);
> + nand->dummy_controller.ops = &fsmc_nand_controller_ops;
> + ret = nand_scan(mtd, 1);
> if (ret)
> goto release_dma_write_chan;
>
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