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Message-Id: <20180722164936.20581-6-marcel@ziswiler.com>
Date: Sun, 22 Jul 2018 18:49:13 +0200
From: Marcel Ziswiler <marcel@...wiler.com>
To: devicetree@...r.kernel.org, linux-tegra@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: Marcel Ziswiler <marcel.ziswiler@...adex.com>,
Thierry Reding <thierry.reding@...il.com>,
Jonathan Hunter <jonathanh@...dia.com>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>
Subject: [PATCH 05/28] ARM: tegra: apalis_t30: reorder pcie properties
From: Marcel Ziswiler <marcel.ziswiler@...adex.com>
Reorder PCIe properties.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@...adex.com>
---
arch/arm/boot/dts/tegra30-apalis.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index 98d702bc3718..0574eda8b3f9 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -16,13 +16,13 @@
pcie@...0 {
avdd-pexa-supply = <&vdd2_reg>;
- vdd-pexa-supply = <&vdd2_reg>;
avdd-pexb-supply = <&vdd2_reg>;
- vdd-pexb-supply = <&vdd2_reg>;
avdd-pex-pll-supply = <&vdd2_reg>;
avdd-plle-supply = <&ldo6_reg>;
- vddio-pex-ctl-supply = <&sys_3v3_reg>;
hvdd-pex-supply = <&sys_3v3_reg>;
+ vddio-pex-ctl-supply = <&sys_3v3_reg>;
+ vdd-pexa-supply = <&vdd2_reg>;
+ vdd-pexb-supply = <&vdd2_reg>;
pci@1,0 {
nvidia,num-lanes = <4>;
--
2.14.4
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