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Message-Id: <20180722212010.3979-7-afaerber@suse.de>
Date: Sun, 22 Jul 2018 23:20:01 +0200
From: Andreas Färber <afaerber@...e.de>
To: linux-mips@...ux-mips.org
Cc: Ralf Baechle <ralf@...ux-mips.org>,
Paul Burton <paul.burton@...s.com>,
James Hogan <jhogan@...nel.org>, linux-kernel@...r.kernel.org,
Andreas Färber <afaerber@...e.de>,
Rahul Bedarkar <rahulbedarkar89@...il.com>,
James Hartley <james.hartley@...drel.com>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>, devicetree@...r.kernel.org
Subject: [PATCH 06/15] MIPS: dts: img: pistachio_marduk: Add 6Lowpan node
The CA8210's clock output is needed for the SPI-UART bridge.
Signed-off-by: Andreas Färber <afaerber@...e.de>
---
arch/mips/boot/dts/img/pistachio_marduk.dts | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/mips/boot/dts/img/pistachio_marduk.dts b/arch/mips/boot/dts/img/pistachio_marduk.dts
index d723b68084c9..b0b6b534a41f 100644
--- a/arch/mips/boot/dts/img/pistachio_marduk.dts
+++ b/arch/mips/boot/dts/img/pistachio_marduk.dts
@@ -158,6 +158,20 @@
<&gpio1 12 GPIO_ACTIVE_HIGH>,
<&gpio1 13 GPIO_ACTIVE_HIGH>,
<&gpio1 14 GPIO_ACTIVE_HIGH>;
+
+ ca8210: sixlowpan@4 {
+ compatible = "cascoda,ca8210";
+ reg = <4>;
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+ irq-gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+
+ extclock-enable;
+ extclock-freq = <16000000>;
+ extclock-gpio = <2>; /* spiuart_clk */
+ #clock-cells = <0>;
+ };
};
&spfi1 {
--
2.16.4
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