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Message-Id: <20180723215404.74296-2-dianders@chromium.org>
Date: Mon, 23 Jul 2018 14:54:03 -0700
From: Douglas Anderson <dianders@...omium.org>
To: sboyd@...nel.org, andy.gross@...aro.org
Cc: tdas@...eaurora.org, grahamr@...eaurora.org,
girishm@...eaurora.org, anischal@...eaurora.org,
bjorn.andersson@...aro.org,
Douglas Anderson <dianders@...omium.org>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>
Subject: [PATCH v2 1/2] clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to header
These clocks will need to be defined in the clock driver and
referenced in device tree files.
Signed-off-by: Douglas Anderson <dianders@...omium.org>
---
Changes in v2: None
include/dt-bindings/clock/qcom,gcc-sdm845.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/dt-bindings/clock/qcom,gcc-sdm845.h b/include/dt-bindings/clock/qcom,gcc-sdm845.h
index f96fc2dbf60e..b8eae5a76503 100644
--- a/include/dt-bindings/clock/qcom,gcc-sdm845.h
+++ b/include/dt-bindings/clock/qcom,gcc-sdm845.h
@@ -194,6 +194,9 @@
#define GPLL4 184
#define GCC_CPUSS_DVM_BUS_CLK 185
#define GCC_CPUSS_GNOC_CLK 186
+#define GCC_QSPI_CORE_CLK_SRC 187
+#define GCC_QSPI_CORE_CLK 188
+#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189
/* GCC Resets */
#define GCC_MMSS_BCR 0
--
2.18.0.233.g985f88cf7e-goog
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