[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20180723155056.GF2494@hirez.programming.kicks-ass.net>
Date: Mon, 23 Jul 2018 17:50:56 +0200
From: Peter Zijlstra <peterz@...radead.org>
To: "Liang, Kan" <kan.liang@...ux.intel.com>
Cc: tglx@...utronix.de, mingo@...hat.com, linux-kernel@...r.kernel.org,
acme@...nel.org, alexander.shishkin@...ux.intel.com,
vincent.weaver@...ne.edu, jolsa@...hat.com, ak@...ux.intel.com
Subject: Re: [PATCH 1/4] x86/perf/intel: Introduce PMU flag for Extended PEBS
On Mon, Jul 23, 2018 at 11:43:56AM -0400, Liang, Kan wrote:
> > So I like PEBS_ALL.. what I don't like is that it seems to be mutually
> > exclusive with PEBS Load Latency.
>
> Right, MSR_PEBS_ENABLE:32-35 is model specific.
Doesn't mean they couldn't have avoided conflicting bits.
> For Atom,
> Goldmont and earlier platform, they are reserved.
> Goldmont Plus, 32-34 are for fixed counter, 35 is reserved.
> For Core,
> from Nehalem to latest 8th, 32-35 are for Load Latency.
Seems rather unfortunate to me. Because PEBS_ALL is good, but since they
took conflicting bits, we'll have yet another variant when/if (I hope
they do) they bring it to Core :/
Powered by blists - more mailing lists