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Message-Id: <20180724104309.21741-15-marcel@ziswiler.com>
Date: Tue, 24 Jul 2018 12:43:08 +0200
From: Marcel Ziswiler <marcel@...wiler.com>
To: devicetree@...r.kernel.org, linux-tegra@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: Marcel Ziswiler <marcel.ziswiler@...adex.com>,
Thierry Reding <thierry.reding@...il.com>,
Jonathan Hunter <jonathanh@...dia.com>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>
Subject: [PATCH 14/15] ARM: tegra: apalis-tk1: reorder cpu dfll clock properties
From: Marcel Ziswiler <marcel.ziswiler@...adex.com>
Reorder CPU DFLL clock properties.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@...adex.com>
---
arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 2 +-
arch/arm/boot/dts/tegra124-apalis.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
index 13486fe407d2..0837af1bf658 100644
--- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
@@ -1925,8 +1925,8 @@
/* CPU DFLL clock */
clock@...10000 {
status = "okay";
- vdd-cpu-supply = <®_vdd_cpu>;
nvidia,i2c-fs-rate = <400000>;
+ vdd-cpu-supply = <®_vdd_cpu>;
};
ahub@...00000 {
diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi
index 77ca508d755e..18e9e9e8b474 100644
--- a/arch/arm/boot/dts/tegra124-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi
@@ -1954,8 +1954,8 @@
/* CPU DFLL clock */
clock@...10000 {
status = "okay";
- vdd-cpu-supply = <®_vdd_cpu>;
nvidia,i2c-fs-rate = <400000>;
+ vdd-cpu-supply = <®_vdd_cpu>;
};
ahub@...00000 {
--
2.14.4
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