linux-kernel - [PATCH 4.4 01/23] MIPS: ath79: fix register address in ath79_ddr_wb

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Message-Id: <20180727100845.236622331@linuxfoundation.org>
Date:   Fri, 27 Jul 2018 12:09:02 +0200
From:   Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To:     linux-kernel@...r.kernel.org
Cc:     Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        stable@...r.kernel.org, Felix Fietkau <nbd@....name>,
        John Crispin <john@...ozen.org>,
        Paul Burton <paul.burton@...s.com>,
        Alban Bedel <albeu@...e.fr>, James Hogan <jhogan@...nel.org>,
        Ralf Baechle <ralf@...ux-mips.org>, linux-mips@...ux-mips.org
Subject: [PATCH 4.4 01/23] MIPS: ath79: fix register address in ath79_ddr_wb_flush()

4.4-stable review patch.  If anyone has any objections, please let me know.

------------------

From: Felix Fietkau <nbd@....name>

commit bc88ad2efd11f29e00a4fd60fcd1887abfe76833 upstream.

ath79_ddr_wb_flush_base has the type void __iomem *, so register offsets
need to be a multiple of 4 in order to access the intended register.

Signed-off-by: Felix Fietkau <nbd@....name>
Signed-off-by: John Crispin <john@...ozen.org>
Signed-off-by: Paul Burton <paul.burton@...s.com>
Fixes: 24b0e3e84fbf ("MIPS: ath79: Improve the DDR controller interface")
Patchwork: https://patchwork.linux-mips.org/patch/19912/
Cc: Alban Bedel <albeu@...e.fr>
Cc: James Hogan <jhogan@...nel.org>
Cc: Ralf Baechle <ralf@...ux-mips.org>
Cc: linux-mips@...ux-mips.org
Cc: stable@...r.kernel.org # 4.2+
Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>

---
 arch/mips/ath79/common.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- a/arch/mips/ath79/common.c
+++ b/arch/mips/ath79/common.c
@@ -58,7 +58,7 @@ EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);
 
 void ath79_ddr_wb_flush(u32 reg)
 {
-	void __iomem *flush_reg = ath79_ddr_wb_flush_base + reg;
+	void __iomem *flush_reg = ath79_ddr_wb_flush_base + (reg * 4);
 
 	/* Flush the DDR write buffer. */
 	__raw_writel(0x1, flush_reg);