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Message-ID: <20180730101317.GE5789@sirena.org.uk>
Date:   Mon, 30 Jul 2018 11:13:17 +0100
From:   Mark Brown <broonie@...nel.org>
To:     Alexandre Belloni <alexandre.belloni@...tlin.com>
Cc:     James Hogan <jhogan@...nel.org>,
        Paul Burton <paul.burton@...s.com>,
        Andy Shevchenko <andy.shevchenko@...il.com>,
        linux-spi@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-mips@...ux-mips.org,
        Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
        Allan Nielsen <allan.nielsen@...rosemi.com>,
        Rob Herring <robh+dt@...nel.org>
Subject: Re: [PATCH v3 2/5] dt-bindings: spi: snps,dw-apb-ssi: document
 Microsemi integration

On Fri, Jul 27, 2018 at 09:53:55PM +0200, Alexandre Belloni wrote:

> +- compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi"
> +- reg : The register base for the controller. For "mscc,<soc>-spi", a second
> +  register set is required (named ICPU_CFG:SPI_MST)

What are valid values for "<soc>"?

Please submit patches using subject lines reflecting the style for the
subsystem.  This makes it easier for people to identify relevant
patches.  Look at what existing commits in the area you're changing are
doing and make sure your subject lines visually resemble what they're
doing.

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