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Message-ID: <20180730153446.GN5789@sirena.org.uk>
Date: Mon, 30 Jul 2018 16:34:46 +0100
From: Mark Brown <broonie@...nel.org>
To: Andreas Färber <afaerber@...e.de>
Cc: linux-mips@...ux-mips.org, Ralf Baechle <ralf@...ux-mips.org>,
Paul Burton <paul.burton@...s.com>,
James Hogan <jhogan@...nel.org>, linux-kernel@...r.kernel.org,
Ionela Voinescu <ionela.voinescu@...tec.com>,
linux-spi@...r.kernel.org
Subject: Re: [PATCH 13/15] spi: img-spfi: RX maximum burst size for DMA is 8
On Sun, Jul 22, 2018 at 11:20:08PM +0200, Andreas Färber wrote:
> From: Ionela Voinescu <ionela.voinescu@...tec.com>
>
> The depth of the FIFOs is 16 bytes. The DMA request line is tied
> to the half full/empty (depending on the use of the TX or RX FIFO)
> threshold. For the TX FIFO, if you set a burst size of 8 (equal to
> half the depth) the first burst goes into FIFO without any issues,
> but due the latency involved (the time the data leaves the DMA
> engine to the time it arrives at the FIFO), the DMA might trigger
> another burst of 8. But given that there is no space for 2 additonal
> bursts of 8, this would result in a failure. Therefore, we have to
> keep the burst size for TX to 4 to accomodate for an extra burst.
This seems like something that should be sent as a bug fix - doesn't it
fix anything? If it is a fix then it should've gone at the start of the
series so it's got no dependencies and could be sent to Linus for the
current release.
> While here, move the burst size setting outside of the if/else branches
> as they have the same value for both 8 and 32 bit data widths.
Though this refactoring probably less so.
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