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Message-ID: <1533015487-60189-11-git-send-email-erin.lo@mediatek.com>
Date: Tue, 31 Jul 2018 13:38:07 +0800
From: Erin Lo <erin.lo@...iatek.com>
To: Matthias Brugger <matthias.bgg@...il.com>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Thomas Gleixner <tglx@...utronix.de>,
Jason Cooper <jason@...edaemon.net>,
Marc Zyngier <marc.zyngier@....com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Stephen Boyd <sboyd@...eaurora.org>
CC: <devicetree@...r.kernel.org>,
srv_heupstream <srv_heupstream@...iatek.com>,
<linux-kernel@...r.kernel.org>, <linux-serial@...r.kernel.org>,
<linux-mediatek@...ts.infradead.org>,
<linux-arm-kernel@...ts.infradead.org>,
<yingjoe.chen@...iatek.com>, <erin.lo@...iatek.com>,
<mars.cheng@...iatek.com>, <eddie.huang@...iatek.com>,
<linux-clk@...r.kernel.org>, Weiyi Lu <weiyi.lu@...iatek.com>
Subject: [PATCH v4 10/10] dts: arm64: mt8183: add uart node
From: Weiyi Lu <weiyi.lu@...iatek.com>
Add uart node with correct uart clocks.
Signed-off-by: Erin Lo <erin.lo@...iatek.com>
Signed-off-by: Weiyi Lu <weiyi.lu@...iatek.com>
---
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 8 ++++++++
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 30 +++++++++++++++++++++++++++++
2 files changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
index 2a3dd5a..9b52559 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
@@ -12,6 +12,10 @@
model = "MediaTek MT8183 evaluation board";
compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
+ aliases {
+ serial0 = &uart0;
+ };
+
memory@...00000 {
device_type = "memory";
reg = <0 0x40000000 0 0x80000000>;
@@ -21,3 +25,7 @@
stdout-path = "serial0:921600n8";
};
};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 6b87a24..c22a2dc 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -170,6 +170,36 @@
#clock-cells = <1>;
};
+ uart0: serial@...02000 {
+ compatible = "mediatek,mt8183-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x1000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart1: serial@...03000 {
+ compatible = "mediatek,mt8183-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x1000>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart2: serial@...04000 {
+ compatible = "mediatek,mt8183-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11004000 0 0x1000>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
audiosys: syscon@...20000 {
compatible = "mediatek,mt8183-audiosys", "syscon";
reg = <0 0x11220000 0 0x1000>;
--
1.9.1
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