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Message-ID: <20180731163741.GA2359@lst.de>
Date: Tue, 31 Jul 2018 18:37:41 +0200
From: Christoph Hellwig <hch@....de>
To: Atish Patra <atish.patra@....com>
Cc: Christoph Hellwig <hch@....de>,
"tglx@...utronix.de" <tglx@...utronix.de>,
"palmer@...ive.com" <palmer@...ive.com>,
"jason@...edaemon.net" <jason@...edaemon.net>,
"marc.zyngier@....com" <marc.zyngier@....com>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
"mark.rutland@....com" <mark.rutland@....com>,
"anup@...infault.org" <anup@...infault.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"aou@...s.berkeley.edu" <aou@...s.berkeley.edu>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
"shorne@...il.com" <shorne@...il.com>
Subject: Re: [PATCH 7/9] irqchip: add a RISC-V PLIC driver
On Fri, Jul 27, 2018 at 05:04:52PM -0700, Atish Patra wrote:
>> +#define MAX_DEVICES 1024
>> +#define MAX_CONTEXTS 15872
>> +
>
> Is there any way we can preserve some of the comments in the original patch
> about memory-mapped control registers or at least a reference where to find
> the register offset calculations?
The comments really do not help to describe a why or how. I'd love to
add a reference to a spec, but I could not find anything that looks
like an authoritative spec for the SiFive PLIC layout.
>> + u32 __iomem *reg = plic_regs + ENABLE_BASE + ctxid * ENABLE_PER_HART;
>
> shouldn't it be
> u32 __iomem *reg = plic_regs + ENABLE_BASE + ctxid * ENABLE_PER_HART +
> (hwirq / 32) * 4;
Yes, it should. Fixed.
>> + if (unlikely(irq <= 0)) {
>> + pr_warn_ratelimited("can't find mapping for hwirq %lu\n",
>> + hwirq);
>
> Ratlimiting the warning message here didn't help as ack_bad_irq() still
> print message still flooded the console without any useful info.
I've dropped the somewhat pointless ack_bad_irq call, thanks.
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