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Message-ID: <20180801200405.GB6422@codeaurora.org>
Date: Wed, 1 Aug 2018 14:04:05 -0600
From: Lina Iyer <ilina@...eaurora.org>
To: Marc Zyngier <marc.zyngier@....com>
Cc: swboyd@...omium.org, evgreen@...omium.org,
linus.walleij@...aro.org, bjorn.andersson@...aro.org,
rplsssn@...eaurora.org, linux-kernel@...r.kernel.org,
linux-arm-msm@...r.kernel.org, rnayak@...eaurora.org,
devicetree@...r.kernel.org
Subject: Re: [PATCH RESEND RFC 2/4] drivers: pinctrl: qcom: add wakeup gpio
map for sdm845
On Wed, Aug 01 2018 at 02:42 -0600, Marc Zyngier wrote:
>On Wed, 01 Aug 2018 03:00:19 +0100,
>Lina Iyer <ilina@...eaurora.org> wrote:
>>
>> Add GPIO to PDC pin map for the SDM845 SoC.
>>
>> Signed-off-by: Lina Iyer <ilina@...eaurora.org>
>> ---
>> drivers/pinctrl/qcom/pinctrl-sdm845.c | 76 +++++++++++++++++++++++++++
>> 1 file changed, 76 insertions(+)
>>
>> diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c
>> index 2ab7a8885757..e93660922dc2 100644
>> --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c
>> +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c
>> @@ -1277,6 +1277,80 @@ static const struct msm_pingroup sdm845_groups[] = {
>> UFS_RESET(ufs_reset, 0x99f000),
>> };
>>
>> +static struct msm_pinctrl_pdc_map sdm845_wakeup_gpios[] = {
>
>[huge array]
>
>> +};
>
>Why isn't that array part of the DT? I'd expect other SoCs to
>eventually use a similar mechanism, no?
>
I agree and it should be.
One place I am thinking is to add it to the DT definition of PDC
controller as a data argument -
tlmm: pinctrl@...000{
[...]
interrupts-extended = <&pdc 30 IRQ_TYPE_LEVEL_HIGH 1>,
<&pdc 31 IRQ_TYPE_LEVEL_HIGH 3>,
<&pdc 32 IRQ_TYPE_LEVEL_HIGH 5>,
^
|--- Provide the GPIO
for the PDC pin here.
};
pdc: interrupt-controller@...0000 {
compatible = "qcom,sdm845-pdc";
reg = <0xb220000 0x30000>;
qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
#interrupt-cells = <3>; <-------- Increase this from 2 ?
interrupt-parent = <&intc>;
interrupt-controller;
};
Would that be acceptable?
Thanks,
Lina
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