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Message-ID: <6ac80566-be1b-3dfc-e6b7-3c38131673ef@kernel.org>
Date: Wed, 1 Aug 2018 01:00:32 -0700
From: Sinan Kaya <okaya@...nel.org>
To: Christoph Hellwig <hch@....de>, okaya@...eaurora.org
Cc: Tony Luck <tony.luck@...el.com>, Fenghua Yu <fenghua.yu@...el.com>,
Arnd Bergmann <arnd@...db.de>, linux-ia64@...r.kernel.org,
linux-arch@...r.kernel.org, linux-kernel@...r.kernel.org,
iommu@...ts.linux-foundation.org
Subject: Re: [PATCH] ia64: fix barrier placement for write* / dma mapping
On 8/1/2018 12:29 AM, Christoph Hellwig wrote:
>> I asked this question to Tony Luck before. If I remember right,
>> his answer was:
>>
>> CPU guarantees outstanding writes to be flushed when a register write
>> instruction is executed and an additional barrier instruction is not
>> needed.
> That would be great. It still doesn't explain the barriers in the
> dma sync routines. Those have been there since the following commit
> in the history tree:
Yeah, I'll let Tony confirm my understanding.
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