linux-kernel - RE: [PATCH V2] x86/speculation: Support Enhanced IBRS on future CPUs

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Message-ID: <FFF73D592F13FD46B8700F0A279B802F47654398@ORSMSX114.amr.corp.intel.com>
Date:   Wed, 1 Aug 2018 08:01:47 +0000
From:   "Prakhya, Sai Praneeth" <sai.praneeth.prakhya@...el.com>
To:     Thomas Gleixner <tglx@...utronix.de>
CC:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "x86@...nel.org" <x86@...nel.org>,
        "Chen, Tim C" <tim.c.chen@...el.com>,
        "Hansen, Dave" <dave.hansen@...el.com>,
        "Shankar, Ravi V" <ravi.v.shankar@...el.com>,
        Ingo Molnar <mingo@...nel.org>
Subject: RE: [PATCH V2] x86/speculation: Support Enhanced IBRS on future CPUs

> > Yes, that makes sense.
> > But on the machine, I see IBRS bit set on all cores. As you said,
> > someone else might be writing the MSR. I will try to find that out and will
> update the patch accordingly.
> >
> > I initially suspected it to be __ssb_select_mitigation() as I have
> > "spec_store_bypass_disable=on" in the kernel command line, but turns out it's
> not so.
> > I will update you more on this.
> 
> There are lots of places like the firmware mitigation stuff and other things which
> write that MSR. And because the bit is set in x86_spec_ctrl_base it will be on at
> some point and stay so.

True! After a bit of experimenting with printk(), I see that it's being set by 
intel_set_ssb_state() during systemd initialization.

> 
> Writing it explicitely at the point where it is set makes it independent of other
> mechanisms which touch that MSR and Just Works.

Yes, that makes sense. I will add an explicit wrmsrl().
Just wanted to have a better understanding of how things work.

Regards,
Sai