linux-kernel - [PATCH 2/3] PCI: Use dedicated Xilinx controller irq number for AER

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Date:   Wed, 1 Aug 2018 22:14:48 +0530
From:   Bharat Kumar Gogada <bharat.kumar.gogada@...inx.com>
To:     <linux-pci@...r.kernel.org>, <linux-kernel@...r.kernel.org>
CC:     <bhelgaas@...gle.com>, <rgummal@...inx.com>,
        Bharat Kumar Gogada <bharat.kumar.gogada@...inx.com>
Subject: [PATCH 2/3] PCI: Use dedicated Xilinx controller irq number for AER

Xilinx ZynqMP PS PCIe does not report AER interrupts using Advanced
Error Interrupt Message Number. The controller has dedicated interrupt line
for reporting PCIe errors along with AER.

Using pci_dev->sysdata of root port to save controller irq number, which
will be used for registering AER irq handler.

Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@...inx.com>
---
 drivers/pci/quirks.c |   29 +++++++++++++++++++++++++++++
 1 files changed, 29 insertions(+), 0 deletions(-)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index f439de8..e666373 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -4753,3 +4753,32 @@ static void quirk_gpu_hda(struct pci_dev *hda)
 			      PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
 			      PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
+
+#if defined(CONFIG_ARCH_ZYNQMP) && defined(CONFIG_PCIE_XILINX_NWL) && \
+	defined(CONFIG_PCIEAER)
+/*
+ * Xilinx ZynqMP PS PCIe does not report AER interrupts using Advanced
+ * Error Interrupt Message Number. The controller has dedicated interrupt line
+ * for reporting PCIe errors along with AER.
+ */
+#include <linux/of.h>
+#include <linux/of_irq.h>
+
+static void quirk_xilinx_aer_irq(struct pci_dev *dev)
+{
+	struct device_node *dev_node;
+
+	if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT &&
+	    pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR)) {
+		dev_node = of_find_compatible_node(NULL, NULL,
+						   "xlnx,nwl-pcie-2.11");
+		if (!dev_node) {
+			dev_err(&dev->dev, "Error could not find ZynqMP PS PCIe node\n");
+			return;
+		}
+
+		dev->sysdata = dev_node->data;
+	}
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_XILINX, PCI_ANY_ID, quirk_xilinx_aer_irq);
+#endif
-- 
1.7.1