linux-kernel - [tip:perf/core] perf vendor events arm64: Update ThunderX2 implementation defined pmu core events

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Message-ID: <tip-b9b77222d4ff6b5bb8f5d87fca20de0910618bb9@git.kernel.org>
Date:   Thu, 2 Aug 2018 01:15:12 -0700
From:   tip-bot for Ganapatrao Kulkarni <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     alexander.shishkin@...ux.intel.com, hpa@...or.com,
        ganapatrao.kulkarni@...ium.com, acme@...hat.com,
        gklkml16@...il.com, tglx@...utronix.de, namhyung@...nel.org,
        linux-kernel@...r.kernel.org, peterz@...radead.org,
        jnair@...iumnetworks.com, jan.glauber@...ium.com, jolsa@...hat.com,
        will.deacon@....com, mark.rutland@....com,
        vadim.lomovtsev@...ium.com, mingo@...nel.org,
        robert.richter@...ium.com
Subject: [tip:perf/core] perf vendor events arm64: Update ThunderX2
 implementation defined pmu core events

Commit-ID:  b9b77222d4ff6b5bb8f5d87fca20de0910618bb9
Gitweb:     https://git.kernel.org/tip/b9b77222d4ff6b5bb8f5d87fca20de0910618bb9
Author:     Ganapatrao Kulkarni <ganapatrao.kulkarni@...ium.com>
AuthorDate: Tue, 31 Jul 2018 15:32:51 +0530
Committer:  Arnaldo Carvalho de Melo <acme@...hat.com>
CommitDate: Tue, 31 Jul 2018 11:28:44 -0300

perf vendor events arm64: Update ThunderX2 implementation defined pmu core events

Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@...ium.com>
Cc: Alexander Shishkin <alexander.shishkin@...ux.intel.com>
Cc: Ganapatrao Kulkarni <gklkml16@...il.com>
Cc: Jan Glauber <jan.glauber@...ium.com>
Cc: Jayachandran C <jnair@...iumnetworks.com>
Cc: Jiri Olsa <jolsa@...hat.com>
Cc: linux-arm-kernel@...ts.infradead.org
Cc: Mark Rutland <mark.rutland@....com>
Cc: Namhyung Kim <namhyung@...nel.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Robert Richter <robert.richter@...ium.com>
Cc: Vadim Lomovtsev <vadim.lomovtsev@...ium.com>
Cc: Will Deacon <will.deacon@....com>
Link: http://lkml.kernel.org/r/20180731100251.23575-1-ganapatrao.kulkarni@cavium.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@...hat.com>
---
 .../arch/arm64/cavium/thunderx2/core-imp-def.json  | 87 +++++++++++++++++++++-
 1 file changed, 84 insertions(+), 3 deletions(-)

diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
index bc03c06c3918..752e47eb6977 100644
--- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
+++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
@@ -11,6 +11,21 @@
     {
         "ArchStdEvent": "L1D_CACHE_REFILL_WR",
     },
+    {
+        "ArchStdEvent": "L1D_CACHE_REFILL_INNER",
+    },
+    {
+        "ArchStdEvent": "L1D_CACHE_REFILL_OUTER",
+    },
+    {
+        "ArchStdEvent": "L1D_CACHE_WB_VICTIM",
+    },
+    {
+        "ArchStdEvent": "L1D_CACHE_WB_CLEAN",
+    },
+    {
+        "ArchStdEvent": "L1D_CACHE_INVAL",
+    },
     {
         "ArchStdEvent": "L1D_TLB_REFILL_RD",
     },
@@ -23,10 +38,76 @@
     {
         "ArchStdEvent": "L1D_TLB_WR",
     },
+    {
+        "ArchStdEvent": "L2D_TLB_REFILL_RD",
+    },
+    {
+        "ArchStdEvent": "L2D_TLB_REFILL_WR",
+    },
+    {
+        "ArchStdEvent": "L2D_TLB_RD",
+    },
+    {
+        "ArchStdEvent": "L2D_TLB_WR",
+    },
     {
         "ArchStdEvent": "BUS_ACCESS_RD",
-   },
-   {
+    },
+    {
         "ArchStdEvent": "BUS_ACCESS_WR",
-   }
+    },
+    {
+        "ArchStdEvent": "MEM_ACCESS_RD",
+    },
+    {
+        "ArchStdEvent": "MEM_ACCESS_WR",
+    },
+    {
+        "ArchStdEvent": "UNALIGNED_LD_SPEC",
+    },
+    {
+        "ArchStdEvent": "UNALIGNED_ST_SPEC",
+    },
+    {
+        "ArchStdEvent": "UNALIGNED_LDST_SPEC",
+    },
+    {
+        "ArchStdEvent": "EXC_UNDEF",
+    },
+    {
+        "ArchStdEvent": "EXC_SVC",
+    },
+    {
+        "ArchStdEvent": "EXC_PABORT",
+    },
+    {
+        "ArchStdEvent": "EXC_DABORT",
+    },
+    {
+        "ArchStdEvent": "EXC_IRQ",
+    },
+    {
+        "ArchStdEvent": "EXC_FIQ",
+    },
+    {
+        "ArchStdEvent": "EXC_SMC",
+    },
+    {
+        "ArchStdEvent": "EXC_HVC",
+    },
+    {
+        "ArchStdEvent": "EXC_TRAP_PABORT",
+    },
+    {
+        "ArchStdEvent": "EXC_TRAP_DABORT",
+    },
+    {
+        "ArchStdEvent": "EXC_TRAP_OTHER",
+    },
+    {
+        "ArchStdEvent": "EXC_TRAP_IRQ",
+    },
+    {
+        "ArchStdEvent": "EXC_TRAP_FIQ",
+    }
 ]