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Message-ID: <1533213288-8771-5-git-send-email-manish.narani@xilinx.com>
Date:   Thu, 2 Aug 2018 18:04:48 +0530
From:   Manish Narani <manish.narani@...inx.com>
To:     <robh+dt@...nel.org>, <mark.rutland@....com>,
        <catalin.marinas@....com>, <will.deacon@....com>,
        <michal.simek@...inx.com>, <bp@...en8.de>, <mchehab@...nel.org>,
        <mdf@...nel.org>, <edgar.iglesias@...inx.com>,
        <shubhrajyoti.datta@...inx.com>,
        <naga.sureshkumar.relli@...inx.com>,
        <bharat.kumar.gogada@...inx.com>, <stefan.krsmanovic@...ios.com>
CC:     <sgoud@...inx.com>, <anirudh@...inx.com>,
        <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-edac@...r.kernel.org>,
        Manish Narani <manish.narani@...inx.com>
Subject: [PATCH v2 4/4] arm64: zynqmp: Add DDRC node

This patch adds ddrc memory controller node in dts. The size mentioned
in dts is 0x30000, because we need to access DDR_QOS INTR registers
located at fd090208 from this driver.

Signed-off-by: Manish Narani <manish.narani@...inx.com>
---
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index a091e6f..7d6a3cf 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -355,6 +355,13 @@
 			xlnx,bus-width = <64>;
 		};
 
+		mc: memory-controller@...70000 {
+			compatible = "xlnx,zynqmp-ddrc-2.40a";
+			reg = <0x0 0xfd070000 0x0 0x30000>;
+			interrupt-parent = <&gic>;
+			interrupts = <0 112 4>;
+		};
+
 		gem0: ethernet@...b0000 {
 			compatible = "cdns,zynqmp-gem", "cdns,gem";
 			status = "disabled";
-- 
2.1.1

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