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Message-ID: <alpine.DEB.2.21.1808030947480.1841@nanos.tec.linutronix.de>
Date: Fri, 3 Aug 2018 09:49:20 +0200 (CEST)
From: Thomas Gleixner <tglx@...utronix.de>
To: Palmer Dabbelt <palmer@...ive.com>
cc: Christoph Hellwig <hch@....de>, jason@...edaemon.net,
marc.zyngier@....com, robh+dt@...nel.org, mark.rutland@....com,
anup@...infault.org, atish.patra@....com,
devicetree@...r.kernel.org, aou@...s.berkeley.edu,
linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
shorne@...il.com
Subject: Re: simplified RISC-V interrupt and clocksource handling v2
On Thu, 2 Aug 2018, Palmer Dabbelt wrote:
> bit of arch/riscv diff here so I don't mind taking it through the RISC-V tree,
> but there's also some irqchip and clocksource stuff as well so I'm not sure if
> that's OK to do.
I have no objections if that goes through the risc-v tree once the DT stuff
is sorted out.
For the clocksource and irqchip bits:
Acked-by: Thomas Gleixner <tglx@...utronix.de>
Thanks,
tglx
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