linux-kernel - RE: [PATCH v2] phy: Add driver for Cadence MHDP DisplayPort SD0801 PHY

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Message-ID: <BYAPR07MB44854DCEA5537DA2D20DC7F0CF230@BYAPR07MB4485.namprd07.prod.outlook.com>
Date:   Fri, 3 Aug 2018 14:46:39 +0000
From:   Scott Telford <stelford@...ence.com>
To:     Kishon Vijay Abraham I <kishon@...com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        Damian Kos <dkos@...ence.com>
Subject: RE: [PATCH v2] phy: Add driver for Cadence MHDP DisplayPort SD0801
 PHY

Hi Kishon,

> -----Original Message-----
> From: Kishon Vijay Abraham I <kishon@...com>
> Sent: 24 July 2018 04:57
> To: Scott Telford <stelford@...ence.com>; linux-kernel@...r.kernel.org;
> linux-arm-kernel@...ts.infradead.org; Damian Kos <dkos@...ence.com>
> Subject: Re: [PATCH v2] phy: Add driver for Cadence MHDP DisplayPort
> SD0801 PHY
> 
[..]
> > +static void cdns_dp_phy_pma_cmn_cfg_25mhz(struct cdns_dp_phy
> *cdns_phy)
> > +{
> > +	/* refclock registers - assumes 25 MHz refclock */
> > +	writel(0x0019, cdns_phy->sd_base + CMN_SSM_BIAS_TMR);
> > +	writel(0x0032, cdns_phy->sd_base + CMN_PLLSM0_PLLPRE_TMR);
> > +	writel(0x00D1, cdns_phy->sd_base + CMN_PLLSM0_PLLLOCK_TMR);
> > +	writel(0x0032, cdns_phy->sd_base + CMN_PLLSM1_PLLPRE_TMR);
> > +	writel(0x00D1, cdns_phy->sd_base + CMN_PLLSM1_PLLLOCK_TMR);
> > +	writel(0x007D, cdns_phy->sd_base + CMN_BGCAL_INIT_TMR);
> > +	writel(0x007D, cdns_phy->sd_base + CMN_BGCAL_ITER_TMR);
> > +	writel(0x0019, cdns_phy->sd_base + CMN_IBCAL_INIT_TMR);
> > +	writel(0x001E, cdns_phy->sd_base + CMN_TXPUCAL_INIT_TMR);
> > +	writel(0x0006, cdns_phy->sd_base + CMN_TXPUCAL_ITER_TMR);
> > +	writel(0x001E, cdns_phy->sd_base + CMN_TXPDCAL_INIT_TMR);
> > +	writel(0x0006, cdns_phy->sd_base + CMN_TXPDCAL_ITER_TMR);
> > +	writel(0x02EE, cdns_phy->sd_base + CMN_RXCAL_INIT_TMR);
> > +	writel(0x0006, cdns_phy->sd_base + CMN_RXCAL_ITER_TMR);
> > +	writel(0x0002, cdns_phy->sd_base + CMN_SD_CAL_INIT_TMR);
> > +	writel(0x0002, cdns_phy->sd_base + CMN_SD_CAL_ITER_TMR);
> > +	writel(0x000E, cdns_phy->sd_base + CMN_SD_CAL_REFTIM_START);
> > +	writel(0x012B, cdns_phy->sd_base + CMN_SD_CAL_PLLCNT_START);
> > +	/* PLL registers */
> > +	writel(0x0409, cdns_phy->sd_base +
> CMN_PDIAG_PLL0_CP_PADJ_M0);
> > +	writel(0x1001, cdns_phy->sd_base +
> CMN_PDIAG_PLL0_CP_IADJ_M0);
> > +	writel(0x0F08, cdns_phy->sd_base +
> CMN_PDIAG_PLL0_FILT_PADJ_M0);
> > +	writel(0x0004, cdns_phy->sd_base + CMN_PLL0_DSM_DIAG_M0);
> > +	writel(0x00FA, cdns_phy->sd_base +
> CMN_PLL0_VCOCAL_INIT_TMR);
> > +	writel(0x0004, cdns_phy->sd_base +
> CMN_PLL0_VCOCAL_ITER_TMR);
> > +	writel(0x00FA, cdns_phy->sd_base +
> CMN_PLL1_VCOCAL_INIT_TMR);
> > +	writel(0x0004, cdns_phy->sd_base +
> CMN_PLL1_VCOCAL_ITER_TMR);
> > +	writel(0x0318, cdns_phy->sd_base +
> CMN_PLL0_VCOCAL_REFTIM_START);
> 
> Are these values that are written just calibration data or are they bitfields
> for a specific setting. If they are not calibration data, then macros should be
> added. 

These are calibration values.

I will post a new revision addressing your other comments shortly.

Regards,
Scott.