linux-kernel - [PATCH v4 2/4] dt: bindings: Document ZynqMP DDRC in Synopsys documentation

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Message-ID: <1533374735-16662-3-git-send-email-manish.narani@xilinx.com>
Date:   Sat, 4 Aug 2018 14:55:33 +0530
From:   Manish Narani <manish.narani@...inx.com>
To:     <robh+dt@...nel.org>, <mark.rutland@....com>,
        <catalin.marinas@....com>, <will.deacon@....com>,
        <michal.simek@...inx.com>, <bp@...en8.de>, <mchehab@...nel.org>,
        <mdf@...nel.org>, <edgar.iglesias@...inx.com>,
        <shubhrajyoti.datta@...inx.com>,
        <naga.sureshkumar.relli@...inx.com>,
        <bharat.kumar.gogada@...inx.com>, <stefan.krsmanovic@...ios.com>
CC:     <sgoud@...inx.com>, <anirudh@...inx.com>,
        <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-edac@...r.kernel.org>,
        Manish Narani <manish.narani@...inx.com>
Subject: [PATCH v4 2/4] dt: bindings: Document ZynqMP DDRC in Synopsys documentation

This patch adds information of ZynqMP DDRC which reports the single bit
errors that are corrected and the double bit errors that are detected.

Signed-off-by: Manish Narani <manish.narani@...inx.com>
---
 .../bindings/memory-controllers/synopsys.txt       | 27 ++++++++++++++++++----
 1 file changed, 22 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
index a43d26d..9d32762 100644
--- a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
@@ -1,15 +1,32 @@
 Binding for Synopsys IntelliDDR Multi Protocol Memory Controller
 
-This controller has an optional ECC support in half-bus width (16-bit)
-configuration. The ECC controller corrects one bit error and detects
-two bit errors.
+The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and 32-bit
+bus width configurations.
+
+The Zynq DDR ECC controller has an optional ECC support in half-bus width
+(16-bit) configuration.
+
+These both ECC controllers correct single bit ECC errors and detect double bit
+ECC errors.
 
 Required properties:
- - compatible: Should be 'xlnx,zynq-ddrc-a05'
- - reg: Base address and size of the controllers memory area
+ - compatible: One of:
+	- 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller
+	- 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller
+ - reg: Should contain DDR controller registers location and length.
+
+Required properties for "xlnx,zynqmp-ddrc-2.40a":
+ - interrupts: Property with a value describing the interrupt number.
 
 Example:
 	memory-controller@...06000 {
 		compatible = "xlnx,zynq-ddrc-a05";
 		reg = <0xf8006000 0x1000>;
 	};
+
+	mc: memory-controller@...70000 {
+		compatible = "xlnx,zynqmp-ddrc-2.40a";
+		reg = <0x0 0xfd070000 0x0 0x30000>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 112 4>;
+	};
-- 
2.1.1