linux-kernel - Re: [PATCH v4 2/4] arm64: dts: rockchip: add GRF GPIO controller to rk3328

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <4016409.aba6YNvtTb@phil>
Date:   Sat, 04 Aug 2018 15:16:01 +0200
From:   Heiko Stuebner <heiko@...ech.de>
To:     djw@...hip.com.cn
Cc:     linux-rockchip@...ts.infradead.org, Wayne Chou <zxf@...hip.com.cn>,
        Simon Xue <xxm@...k-chips.com>,
        David Wu <david.wu@...k-chips.com>,
        Finley Xiao <finley.xiao@...k-chips.com>,
        devicetree@...r.kernel.org,
        Klaus Goger <klaus.goger@...obroma-systems.com>,
        Sugar Zhang <sugar.zhang@...k-chips.com>,
        linux-kernel@...r.kernel.org, Robin Murphy <robin.murphy@....com>,
        Rob Herring <robh+dt@...nel.org>,
        Rocky Hao <rocky.hao@...k-chips.com>,
        Will Deacon <will.deacon@....com>,
        Mark Rutland <mark.rutland@....com>,
        Catalin Marinas <catalin.marinas@....com>,
        linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v4 2/4] arm64: dts: rockchip: add GRF GPIO controller to rk3328

Hi Levin,

Am Dienstag, 31. Juli 2018, 07:59:20 CEST schrieb djw@...hip.com.cn:
> From: Levin Du <djw@...hip.com.cn>
> 
> Adding a GRF GPIO controller labled "grf_gpio" to rk3328, currently
> providing access to the GPIO_MUTE pin, which is manupulated by the
> GRF_SOC_CON10 register.
> 
> The GPIO_MUTE pin is referred to as <&grf_gpio 0>.
> 
> Signed-off-by: Levin Du <djw@...hip.com.cn>

applied to my dts64 branch, with 2 changes:
- reordered, please sort nodes without address alphabetically
- removed default disabled status
  The controlled pin is always present on the soc, so doesn't need
  to be enabled on a per-board level


Heiko