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Message-Id: <20180804082319.5711-5-hch@lst.de>
Date: Sat, 4 Aug 2018 10:23:15 +0200
From: Christoph Hellwig <hch@....de>
To: tglx@...utronix.de, palmer@...ive.com, jason@...edaemon.net,
marc.zyngier@....com, robh+dt@...nel.org, mark.rutland@....com
Cc: anup@...infault.org, atish.patra@....com,
devicetree@...r.kernel.org, aou@...s.berkeley.edu,
linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
shorne@...il.com
Subject: [PATCH 4/8] RISC-V: add a definition for the SIE SEIE bit
This mirrors the SIE_SSIE and SETE bits that are used in a similar
fashion.
Signed-off-by: Christoph Hellwig <hch@....de>
---
arch/riscv/include/asm/csr.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 421fa3585798..28a0d1cb374c 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -54,6 +54,7 @@
/* Interrupt Enable and Interrupt Pending flags */
#define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */
#define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */
+#define SIE_SEIE _AC(0x00000200, UL) /* External Interrupt Enable */
#define EXC_INST_MISALIGNED 0
#define EXC_INST_ACCESS 1
--
2.18.0
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