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Message-ID: <2D1B8773-0019-458A-8C7E-20077AA27AD4@aosc.io>
Date:   Tue, 07 Aug 2018 15:19:33 +0800
From:   Icenowy Zheng <icenowy@...c.io>
To:     Jagan Teki <jagan@...rulasolutions.com>,
        Maxime Ripard <maxime.ripard@...e-electrons.com>,
        Chen-Yu Tsai <wens@...e.org>
CC:     devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org, linux-sunxi@...glegroups.com
Subject: Re: [PATCH] arm64: allwinner: h6: orangepi-one-plus: Add Ethernet support



于 2018年8月7日 GMT+08:00 下午3:18:39, Jagan Teki <jagan@...rulasolutions.com> 写到:
>Add Ethernet support for orangepi-one-plus board,
>- Ethernet port connected via RTL8211E PHY
>- GMAC_EN is connected via PD6
>- GMAC-3V supplied from ALDO2 regulator

Is the prequisite patchset merged?

>
>Signed-off-by: Jagan Teki <jagan@...rulasolutions.com>
>---
> .../allwinner/sun50i-h6-orangepi-one-plus.dts | 29 +++++++++++++++++++
> 1 file changed, 29 insertions(+)
>
>diff --git
>a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts
>b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts
>index 0612c19cd994..eca5b7ea0d6d 100644
>--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts
>+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts
>@@ -21,6 +21,35 @@
> 	chosen {
> 		stdout-path = "serial0:115200n8";
> 	};
>+
>+	reg_gmac_3v3: gmac-3v3 {
>+		compatible = "regulator-fixed";
>+		regulator-name = "vcc-gmac-3v3";
>+		regulator-min-microvolt = <3300000>;
>+		regulator-max-microvolt = <3300000>;
>+		startup-delay-us = <100000>;
>+		enable-active-high;
>+		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
>+		vin-supply = <&reg_aldo2>;
>+	};
>+};
>+
>+&emac {
>+	pinctrl-names = "default";
>+	pinctrl-0 = <&ext_rgmii_pins>;
>+	phy-mode = "rgmii";
>+	phy-handle = <&ext_rgmii_phy>;
>+	phy-supply = <&reg_gmac_3v3>;
>+	allwinner,rx-delay-ps = <200>;
>+	allwinner,tx-delay-ps = <200>;
>+	status = "okay";
>+};
>+
>+&mdio {
>+	ext_rgmii_phy: ethernet-phy@1 {
>+		compatible = "ethernet-phy-ieee802.3-c22";
>+		reg = <1>;
>+	};
> };
> 
> &mmc0 {

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