linux-kernel - Re: [PATCH 0/9] Add Reset Controller support for Actions Semi Owl SoCs

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20180807184710.GA26423@rob-hp-laptop>
Date:   Tue, 7 Aug 2018 12:47:10 -0600
From:   Rob Herring <robh@...nel.org>
To:     Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
        Andreas Färber <afaerber@...e.de>
Cc:     p.zabel@...gutronix.de, mturquette@...libre.com, sboyd@...nel.org,
        linux-clk@...r.kernel.org, liuwei@...ions-semi.com,
        mp-cs@...ions-semi.com, 96boards@...obotics.com,
        devicetree@...r.kernel.org, daniel.thompson@...aro.org,
        amit.kucheria@...aro.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org, hzhang@...obotics.com,
        bdong@...obotics.com, manivannanece23@...il.com,
        thomas.liau@...ions-semi.com, jeff.chen@...ions-semi.com,
        pn@...x.de, edgar.righi@...tec.org.br, sravanhome@...il.com
Subject: Re: [PATCH 0/9] Add Reset Controller support for Actions Semi Owl
 SoCs

On Mon, Jul 30, 2018 at 08:41:31PM +0530, Manivannan Sadhasivam wrote:
> Hi Andreas,
> 
> On Mon, Jul 30, 2018 at 12:26:07PM +0200, Andreas Färber wrote:
> > Hi Mani,
> > 
> > Am 27.07.2018 um 20:45 schrieb Manivannan Sadhasivam:
> > > This patchset adds Reset Controller (RMU) support for Actions Semi
> > > Owl SoCs, S900 and S700. For the Owl SoCs, RMU has been integrated into
> > > the clock subsystem in hardware. Hence, in software we integrate RMU
> > > support into common clock driver inorder to maintain compatibility.
> > 
> > Can this not be placed into drivers/reset/ by using mfd-simple with a
> > sub-node in DT?

That is exactly what I tell folks not to do. Design the DT based on h/w 
blocks, not current desired driver split for some OS.

> Actually I was not sure where to place this reset controller driver. When I
> looked into other similar ones such as sunxi, they just integrated into the
> clk subsystem. So I just chose that path. But yeah, this is hacky!
> 
> But this RMU is not MFD by any means. Since the CMU (Clock) and RMU (Reset)
> are two separate IPs inside SoC, we shouldn't describe it as a MFD driver. Since
> RMU has only 2 registers, the HW designers decided to use up the CMU memory
> map. So, maybe syscon would be best option I think. What is your opinion?

If there's nothing shared then it is not a syscon. If you can create 
separate address ranges, then 2 nodes is probably okay. If the registers 
are all mixed up, then 1 node.

Rob