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Message-ID: <ab2a113620123cb71364b6ae89328ae2fca49821.camel@buserror.net>
Date: Tue, 07 Aug 2018 16:13:58 -0500
From: Scott Wood <oss@...error.net>
To: Bharat Bhushan <Bharat.Bhushan@....com>, benh@...nel.crashing.org,
paulus@...ba.org, mpe@...erman.id.au, galak@...nel.crashing.org,
mark.rutland@....com, kstewart@...uxfoundation.org,
gregkh@...uxfoundation.org, devicetree@...r.kernel.org,
linuxppc-dev@...ts.ozlabs.org, linux-kernel@...r.kernel.org
Cc: robh@...nel.org, keescook@...omium.org, tyreld@...ux.vnet.ibm.com,
joe@...ches.com
Subject: Re: [RFC 5/5] powerpc/fsl: Add supported-irq-ranges for P2020
On Fri, 2018-07-27 at 15:18 +0530, Bharat Bhushan wrote:
> MPIC on NXP (Freescale) P2020 supports following irq
> ranges:
> > 0 - 11 (External interrupt)
> > 16 - 79 (Internal interrupt)
> > 176 - 183 (Messaging interrupt)
> > 224 - 231 (Shared message signaled interrupt)
Why don't you convert to the 4-cell interrupt specifiers that make dealing
with these ranges less error-prone?
> diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
> b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
> index 1006950..49ff348 100644
> --- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
> +++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
> @@ -57,6 +57,11 @@ void __init mpc85xx_rdb_pic_init(void)
> MPIC_BIG_ENDIAN |
> MPIC_SINGLE_DEST_CPU,
> 0, 256, " OpenPIC ");
> + } else if (of_machine_is_compatible("fsl,P2020RDB-PC")) {
> + mpic = mpic_alloc(NULL, 0,
> + MPIC_BIG_ENDIAN |
> + MPIC_SINGLE_DEST_CPU,
> + 0, 0, " OpenPIC ");
> } else {
> mpic = mpic_alloc(NULL, 0,
> MPIC_BIG_ENDIAN |
I don't think we want to grow a list of every single revision of every board
in these platform files.
-Scott
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