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Date:   Wed, 8 Aug 2018 01:28:37 +0000
From:   "Luck, Tony" <tony.luck@...el.com>
To:     "Chatre, Reinette" <reinette.chatre@...el.com>,
        Peter Zijlstra <peterz@...radead.org>
CC:     "Hansen, Dave" <dave.hansen@...el.com>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "Yu, Fenghua" <fenghua.yu@...el.com>,
        "vikas.shivappa@...ux.intel.com" <vikas.shivappa@...ux.intel.com>,
        "Hindman, Gavin" <gavin.hindman@...el.com>,
        "Joseph, Jithu" <jithu.joseph@...el.com>,
        "hpa@...or.com" <hpa@...or.com>, "x86@...nel.org" <x86@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH 0/2] x86/intel_rdt and perf/x86: Fix lack of
 coordination with perf

Would it help to call routines to read the "before" values of the counter
twice. The first time to preload the cache with anything needed to execute
the perf code path.

>> In an attempt to improve the accuracy of the above I modified it to the
>> following:
>>
>> /* create the two events as before in "enabled" state */
>> l2_hit_pmcnum = l2_hit_event->hw.event_base_rdpmc;
>> l2_miss_pmcnum = l2_miss_event->hw.event_base_rdpmc;
>> local_irq_disable();
>> /* disable hw prefetchers */
>> /* init local vars to loop through pseudo-locked mem
      * may take some misses in the perf code
      */
     l2_hits_before = native_read_pmc(l2_hit_pmcnum);
     l2_miss_before = native_read_pmc(l2_miss_pmcnum);
     /* Read counters again, hope no new misses here */
>> l2_hits_before = native_read_pmc(l2_hit_pmcnum);
>> l2_miss_before = native_read_pmc(l2_miss_pmcnum);
>> /* loop through pseudo-locked mem */
>> l2_hits_after = native_read_pmc(l2_hit_pmcnum);
>> l2_miss_after = native_read_pmc(l2_miss_pmcnum);
>> /* enable hw prefetchers */
>> local_irq_enable();

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