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Date: Wed, 8 Aug 2018 15:55:54 +0000
From: "Luck, Tony" <tony.luck@...el.com>
To: Peter Zijlstra <peterz@...radead.org>,
"Chatre, Reinette" <reinette.chatre@...el.com>
CC: "Hansen, Dave" <dave.hansen@...el.com>,
"tglx@...utronix.de" <tglx@...utronix.de>,
"mingo@...hat.com" <mingo@...hat.com>,
"Yu, Fenghua" <fenghua.yu@...el.com>,
"vikas.shivappa@...ux.intel.com" <vikas.shivappa@...ux.intel.com>,
"Hindman, Gavin" <gavin.hindman@...el.com>,
"Joseph, Jithu" <jithu.joseph@...el.com>,
"hpa@...or.com" <hpa@...or.com>, "x86@...nel.org" <x86@...nel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH 0/2] x86/intel_rdt and perf/x86: Fix lack of
coordination with perf
> So _why_ doesn't this work? As said by Tony, that first call should
> prime the caches, so the second and third calls should not generate any
> misses.
How much code/data is involved? If there is a lot, then you may be unlucky
with cache coloring and the later parts of the "prime the caches" code path
may evict some lines loaded in the early parts.
-Tony
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