linux-kernel - Re: [PATCH v2 03/18] dt-bindings: clk: Add documentation of grx500 clock controller

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Wed, 8 Aug 2018 11:08:48 +0800
From:   yixin zhu <yixin.zhu@...ux.intel.com>
To:     Rob Herring <robh+dt@...nel.org>,
        Songjun Wu <songjun.wu@...ux.intel.com>
Cc:     hua.ma@...ux.intel.com, chuanhua.lei@...ux.intel.com,
        qi-ming.wu@...el.com, Linux-MIPS <linux-mips@...ux-mips.org>,
        linux-clk <linux-clk@...r.kernel.org>,
        "open list:SERIAL DRIVERS" <linux-serial@...r.kernel.org>,
        devicetree@...r.kernel.org,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Mark Rutland <mark.rutland@....com>
Subject: Re: [PATCH v2 03/18] dt-bindings: clk: Add documentation of grx500
 clock controller



On 8/6/2018 11:18 PM, Rob Herring wrote:
> On Thu, Aug 2, 2018 at 9:03 PM Songjun Wu <songjun.wu@...ux.intel.com> wrote:
>> From: Yixin Zhu <yixin.zhu@...ux.intel.com>
>>
>> This patch adds binding documentation for grx500 clock controller.
>>
>> Signed-off-by: YiXin Zhu <yixin.zhu@...ux.intel.com>
>> Signed-off-by: Songjun Wu <songjun.wu@...ux.intel.com>
>> ---
>>
>> Changes in v2:
>> - Rewrite clock driver's dt-binding document according to Rob Herring's
>>    comments.
>> - Simplify device tree docoment, remove some clock description.
>>
>>   .../devicetree/bindings/clock/intel,grx500-clk.txt | 39 ++++++++++++++++++++++
> Please match the compatible string: intel,grx500-cgu.txt
Will update to use same name.

>
>>   1 file changed, 39 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/clock/intel,grx500-clk.txt
>>
>> diff --git a/Documentation/devicetree/bindings/clock/intel,grx500-clk.txt b/Documentation/devicetree/bindings/clock/intel,grx500-clk.txt
>> new file mode 100644
>> index 000000000000..e54e1dad9196
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/intel,grx500-clk.txt
>> @@ -0,0 +1,39 @@
>> +Device Tree Clock bindings for grx500 PLL controller.
>> +
>> +This binding uses the common clock binding:
>> +       Documentation/devicetree/bindings/clock/clock-bindings.txt
>> +
>> +The grx500 clock controller supplies clock to various controllers within the
>> +SoC.
>> +
>> +Required properties for clock node
>> +- compatible: Should be "intel,grx500-cgu".
>> +- reg: physical base address of the controller and length of memory range.
>> +- #clock-cells: should be 1.
>> +
>> +Optional Propteries:
>> +- intel,osc-frequency: frequency of the osc clock.
>> +if missing, driver will use clock rate defined in the driver.
> This should use a fixed-clock node instead.
Yes, This is a fixed clock node registered in driver code.
The frequency of the fixed clock is designed to be overwritten by device 
tree in case some one verify
clock driver in the emulation platform or in some cases frequency other 
than driver defined one is preferred.
These kinds of cases are very rare. But I feel it would be better to 
have a way to use customized frequency.
The frequency defined in device tree will overwritten driver defined 
frequency before registering fixed-clock node.

>> +
>> +Example: Clock controller node:
>> +
>> +       cgu: cgu@...00000 {
>> +                compatible = "intel,grx500-cgu", "syscon";
>> +               reg = <0x16200000 0x200>;
>> +               #clock-cells = <1>;
>> +       };
>> +
>> +
>> +Example: UART controller node that consumes the clock generated by clock
>> +       controller.
>> +
>> +       asc0: serial@...00000 {
>> +               compatible = "lantiq,asc";
>> +               reg = <0x16600000 0x100000>;
>> +               interrupt-parent = <&gic>;
>> +               interrupts = <GIC_SHARED 103 IRQ_TYPE_LEVEL_HIGH>,
>> +                       <GIC_SHARED 105 IRQ_TYPE_LEVEL_HIGH>,
>> +                       <GIC_SHARED 106 IRQ_TYPE_LEVEL_HIGH>;
>> +               clocks = <&cgu CLK_SSX4>, <&cgu GCLK_UART>;
>> +               clock-names = "freq", "asc";
>> +       };
>> --
>> 2.11.0
>>