linux-kernel - Re: [PATCH 1/8] dt-bindings: mmc: Add DQS trim value to Tegra SDHCI

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Thu, 9 Aug 2018 14:45:15 +0300
From:   Aapo Vienamo <avienamo@...dia.com>
To:     Thierry Reding <thierry.reding@...il.com>
CC:     Ulf Hansson <ulf.hansson@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Jonathan Hunter <jonathanh@...dia.com>,
        Adrian Hunter <adrian.hunter@...el.com>,
        "Mikko Perttunen" <mperttunen@...dia.com>,
        <linux-mmc@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-tegra@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/8] dt-bindings: mmc: Add DQS trim value to Tegra SDHCI

On Thu, 9 Aug 2018 13:36:09 +0200
Thierry Reding <thierry.reding@...il.com> wrote:

> On Tue, Aug 07, 2018 at 04:59:57PM +0300, Aapo Vienamo wrote:
> > Document HS400 DQS trim value device tree property.
> > 
> > Signed-off-by: Aapo Vienamo <avienamo@...dia.com>
> > ---
> >  Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> > index 3c7960a..7d294f3 100644
> > --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> > +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> > @@ -72,6 +72,7 @@ Optional properties for Tegra210 and Tegra186:
> >    trimmer value for non-tunable modes.
> >  - nvidia,default-trim : Specify the default outbound clock trimmer
> >    value.
> > +- nvidia,dqs-trim : Specify DQS trim value for HS400 timing
> >  
> >    Notes on the pad calibration pull up and pulldown offset values:
> >      - The property values are drive codes which are programmed into the
> > @@ -88,6 +89,8 @@ Optional properties for Tegra210 and Tegra186:
> >      - The values are programmed to the Vendor Clock Control Register.
> >        Please refer to the reference manual of the SoC for correct
> >        values.
> > +    - The DQS trim values are only used on controllers which support
> > +      HS400 timing.  
> 
> One of these additions says "DQS trim values", the other says "DQS trim
> value". It is unclear from the above how many values there are. I think
> this should be more explicit. Also, I don't see why the note about which
> controllers the DQS trim value(s) applies to is in a separate paragraph.
> Couldn't it be moved to the property description?

It's a single value. The plural form is a mistake.

> Also, I think the bindings should specify which generations of Tegra do
> support HS400. Where else are people supposed to find that information?

This property is under the "Optional properties for Tegra210 and
Tegra186" section and it only applies for the said generations.

 -Aapo