linux-kernel - Re: [PATCH 5/8] arm64: dts: tegra186: Add SDMMC4 DQS trim value

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20180809150226.64657f56@dhcp-10-21-25-168>
Date:   Thu, 9 Aug 2018 15:02:26 +0300
From:   Aapo Vienamo <avienamo@...dia.com>
To:     Thierry Reding <thierry.reding@...il.com>
CC:     Ulf Hansson <ulf.hansson@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Jonathan Hunter <jonathanh@...dia.com>,
        Adrian Hunter <adrian.hunter@...el.com>,
        "Mikko Perttunen" <mperttunen@...dia.com>,
        <linux-mmc@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-tegra@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 5/8] arm64: dts: tegra186: Add SDMMC4 DQS trim value

On Thu, 9 Aug 2018 13:49:22 +0200
Thierry Reding <thierry.reding@...il.com> wrote:

> On Tue, Aug 07, 2018 at 05:00:01PM +0300, Aapo Vienamo wrote:
> > Add the HS400 DQS trim value for Tegra186 SDMMC4.
> > 
> > Signed-off-by: Aapo Vienamo <avienamo@...dia.com>
> > ---
> >  arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> > index 6e9ef26..9e07bc6 100644
> > --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> > +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> > @@ -313,6 +313,7 @@
> >  		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
> >  		nvidia,default-tap = <0x5>;
> >  		nvidia,default-trim = <0x9>;
> > +		nvidia,dqs-trim = <63>;
> >  		status = "disabled";
> >  	};
> >    
> 
> Isn't this technically dependent on the board layout and as such would
> belong in the board DTS file? Or does this value work on all existing
> Tegra186 platforms?

This value is specified as part of the controller initialization
sequence in the TRM. I've understood that this (and other tap and trim)
value(s) are used for compensating the propagation delay differences
that are caused by the internal SoC layout.

 -Aapo