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Message-ID: <201808100359.v5cZEx2I%fengguang.wu@intel.com>
Date: Fri, 10 Aug 2018 03:33:11 +0800
From: kbuild test robot <lkp@...el.com>
To: Stephen Boyd <swboyd@...omium.org>
Cc: kbuild-all@...org, Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
linux-kernel@...r.kernel.org,
Wei-Ning Huang <wnhuang@...omium.org>,
Julius Werner <jwerner@...omium.org>,
Brian Norris <briannorris@...omium.org>,
Samuel Holland <samuel@...lland.org>,
Sudeep Holla <Sudeep.Holla@....com>
Subject: Re: [PATCH v2 2/2] firmware: coreboot: Collapse platform drivers
into bus core
Hi Stephen,
I love your patch! Yet something to improve:
[auto build test ERROR on linus/master]
[also build test ERROR on v4.18-rc8 next-20180808]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Stephen-Boyd/firmware-coreboot-Fix-probe-and-simplify-code/20180810-015624
config: mips-allmodconfig (attached as .config)
compiler: mips-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.2.0 make.cross ARCH=mips
All error/warnings (new ones prefixed by >>):
In file included from arch/mips/include/asm/page.h:194:0,
from include/linux/mmzone.h:21,
from include/linux/gfp.h:6,
from include/linux/slab.h:15,
from include/linux/resource_ext.h:19,
from include/linux/acpi.h:26,
from drivers/firmware//google/coreboot_table.c:19:
drivers/firmware//google/coreboot_table.c: In function 'coreboot_table_probe':
>> arch/mips/include/asm/io.h:277:35: error: '_page_cachable_default' undeclared (first use in this function)
__ioremap_mode((offset), (size), _page_cachable_default)
^
>> arch/mips/include/asm/io.h:278:23: note: in expansion of macro 'ioremap_cachable'
#define ioremap_cache ioremap_cachable
^~~~~~~~~~~~~~~~
>> drivers/firmware//google/coreboot_table.c:158:11: note: in expansion of macro 'ioremap_cache'
header = ioremap_cache(phyaddr, sizeof(*header));
^~~~~~~~~~~~~
arch/mips/include/asm/io.h:277:35: note: each undeclared identifier is reported only once for each function it appears in
__ioremap_mode((offset), (size), _page_cachable_default)
^
>> arch/mips/include/asm/io.h:278:23: note: in expansion of macro 'ioremap_cachable'
#define ioremap_cache ioremap_cachable
^~~~~~~~~~~~~~~~
>> drivers/firmware//google/coreboot_table.c:158:11: note: in expansion of macro 'ioremap_cache'
header = ioremap_cache(phyaddr, sizeof(*header));
^~~~~~~~~~~~~
--
In file included from arch/mips/include/asm/page.h:194:0,
from include/linux/mmzone.h:21,
from include/linux/gfp.h:6,
from include/linux/slab.h:15,
from include/linux/resource_ext.h:19,
from include/linux/acpi.h:26,
from drivers/firmware/google/coreboot_table.c:19:
drivers/firmware/google/coreboot_table.c: In function 'coreboot_table_probe':
>> arch/mips/include/asm/io.h:277:35: error: '_page_cachable_default' undeclared (first use in this function)
__ioremap_mode((offset), (size), _page_cachable_default)
^
>> arch/mips/include/asm/io.h:278:23: note: in expansion of macro 'ioremap_cachable'
#define ioremap_cache ioremap_cachable
^~~~~~~~~~~~~~~~
drivers/firmware/google/coreboot_table.c:158:11: note: in expansion of macro 'ioremap_cache'
header = ioremap_cache(phyaddr, sizeof(*header));
^~~~~~~~~~~~~
arch/mips/include/asm/io.h:277:35: note: each undeclared identifier is reported only once for each function it appears in
__ioremap_mode((offset), (size), _page_cachable_default)
^
>> arch/mips/include/asm/io.h:278:23: note: in expansion of macro 'ioremap_cachable'
#define ioremap_cache ioremap_cachable
^~~~~~~~~~~~~~~~
drivers/firmware/google/coreboot_table.c:158:11: note: in expansion of macro 'ioremap_cache'
header = ioremap_cache(phyaddr, sizeof(*header));
^~~~~~~~~~~~~
vim +/_page_cachable_default +277 arch/mips/include/asm/io.h
^1da177e include/asm-mips/io.h Linus Torvalds 2005-04-16 260
^1da177e include/asm-mips/io.h Linus Torvalds 2005-04-16 261 /*
778e2ac5 include/asm-mips/io.h Ralf Baechle 2006-02-28 262 * ioremap_cachable - map bus memory into CPU space
778e2ac5 include/asm-mips/io.h Ralf Baechle 2006-02-28 263 * @offset: bus address of the memory
778e2ac5 include/asm-mips/io.h Ralf Baechle 2006-02-28 264 * @size: size of the resource to map
778e2ac5 include/asm-mips/io.h Ralf Baechle 2006-02-28 265 *
778e2ac5 include/asm-mips/io.h Ralf Baechle 2006-02-28 266 * ioremap_nocache performs a platform specific sequence of operations to
778e2ac5 include/asm-mips/io.h Ralf Baechle 2006-02-28 267 * make bus memory CPU accessible via the readb/readw/readl/writeb/
778e2ac5 include/asm-mips/io.h Ralf Baechle 2006-02-28 268 * writew/writel functions and the other mmio helpers. The returned
778e2ac5 include/asm-mips/io.h Ralf Baechle 2006-02-28 269 * address is not guaranteed to be usable directly as a virtual
778e2ac5 include/asm-mips/io.h Ralf Baechle 2006-02-28 270 * address.
778e2ac5 include/asm-mips/io.h Ralf Baechle 2006-02-28 271 *
778e2ac5 include/asm-mips/io.h Ralf Baechle 2006-02-28 272 * This version of ioremap ensures that the memory is marked cachable by
778e2ac5 include/asm-mips/io.h Ralf Baechle 2006-02-28 273 * the CPU. Also enables full write-combining. Useful for some
778e2ac5 include/asm-mips/io.h Ralf Baechle 2006-02-28 274 * memory-like regions on I/O busses.
778e2ac5 include/asm-mips/io.h Ralf Baechle 2006-02-28 275 */
778e2ac5 include/asm-mips/io.h Ralf Baechle 2006-02-28 276 #define ioremap_cachable(offset, size) \
35133692 include/asm-mips/io.h Chris Dearman 2007-09-19 @277 __ioremap_mode((offset), (size), _page_cachable_default)
a68f3768 arch/mips/include/asm/io.h Maciej W. Rozycki 2016-01-09 @278 #define ioremap_cache ioremap_cachable
778e2ac5 include/asm-mips/io.h Ralf Baechle 2006-02-28 279
:::::: The code at line 277 was first introduced by commit
:::::: 351336929ccf222ae38ff0cb7a8dd5fd5c6236a0 [MIPS] Allow setting of the cache attribute at run time.
:::::: TO: Chris Dearman <chris@...s.com>
:::::: CC: Ralf Baechle <ralf@...ux-mips.org>
---
0-DAY kernel test infrastructure Open Source Technology Center
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