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Message-Id: <20180809214654.21308-1-paul@crapouillou.net>
Date: Thu, 9 Aug 2018 23:46:52 +0200
From: Paul Cercueil <paul@...pouillou.net>
To: Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Thierry Reding <thierry.reding@...il.com>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Wim Van Sebroeck <wim@...ux-watchdog.org>,
Guenter Roeck <linux@...ck-us.net>,
Ralf Baechle <ralf@...ux-mips.org>,
Paul Burton <paul.burton@...s.com>,
James Hogan <jhogan@...nel.org>,
Jonathan Corbet <corbet@....net>,
Lee Jones <lee.jones@...aro.org>,
Mathieu Malaterre <malat@...ian.org>,
Ezequiel Garcia <ezequiel@...labora.co.uk>
Cc: linux-pwm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-watchdog@...r.kernel.org,
linux-mips@...ux-mips.org, linux-doc@...r.kernel.org,
linux-clk@...r.kernel.org, Paul Cercueil <paul@...pouillou.net>
Subject: [PATCH v6 22/24] MIPS: CI20: Reduce system timer and clocksource to 3 MHz
The default clock (48 MHz) is too fast for the system timer, which fails
to report time accurately.
Signed-off-by: Paul Cercueil <paul@...pouillou.net>
---
arch/mips/boot/dts/ingenic/ci20.dts | 6 ++++++
1 file changed, 6 insertions(+)
v5: New patch
v6: Set also the rate for the clocksource channel's clock
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
index 50cff3cbcc6d..f64d32443097 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -238,3 +238,9 @@
bias-disable;
};
};
+
+&tcu {
+ /* 3 MHz for the system timer and clocksource */
+ assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>;
+ assigned-clock-rates = <3000000>, <3000000>;
+};
--
2.11.0
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