linux-kernel - [PATCH v3 05/17] x86/perfctr: return perf counter and event selection bit offset

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Message-Id: <3c687a337c87923884eb4ba11cf55cbe0203b878.1533989492.git.puwen@hygon.cn>
Date:   Sat, 11 Aug 2018 21:27:07 +0800
From:   Pu Wen <puwen@...on.cn>
To:     tglx@...utronix.de, mingo@...hat.com, hpa@...or.com,
        x86@...nel.org, thomas.lendacky@....com, bp@...en8.de,
        pbonzini@...hat.com
Cc:     linux-kernel@...r.kernel.org, linux-arch@...r.kernel.org,
        Pu Wen <puwen@...on.cn>
Subject: [PATCH v3 05/17] x86/perfctr: return perf counter and event selection bit offset

Hygon Dhyana shares similar perfctr arch with AMD family 17h.
It returns the bit offset of the performance counter register and the
event selection register for Hygon CPU in the similar way as AMD does.

Signed-off-by: Pu Wen <puwen@...on.cn>
---
 arch/x86/kernel/cpu/perfctr-watchdog.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/x86/kernel/cpu/perfctr-watchdog.c b/arch/x86/kernel/cpu/perfctr-watchdog.c
index d389083..9556930 100644
--- a/arch/x86/kernel/cpu/perfctr-watchdog.c
+++ b/arch/x86/kernel/cpu/perfctr-watchdog.c
@@ -46,6 +46,7 @@ static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
 {
 	/* returns the bit offset of the performance counter register */
 	switch (boot_cpu_data.x86_vendor) {
+	case X86_VENDOR_HYGON:
 	case X86_VENDOR_AMD:
 		if (msr >= MSR_F15H_PERF_CTR)
 			return (msr - MSR_F15H_PERF_CTR) >> 1;
@@ -74,6 +75,7 @@ static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
 {
 	/* returns the bit offset of the event selection register */
 	switch (boot_cpu_data.x86_vendor) {
+	case X86_VENDOR_HYGON:
 	case X86_VENDOR_AMD:
 		if (msr >= MSR_F15H_PERF_CTL)
 			return (msr - MSR_F15H_PERF_CTL) >> 1;
-- 
2.7.4