linux-kernel - Re: [PATCH 1/7] dt-bindings: Add DT bindings documentation for Allwinner Thermal Sensor Controller

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20180814192053.GA28118@rob-hp-laptop>
Date:   Tue, 14 Aug 2018 13:20:53 -0600
From:   Rob Herring <robh@...nel.org>
To:     Emmanuel Vadot <manu@...ebsd.org>
Cc:     rui.zhang@...el.com, edubezval@...il.com, mark.rutland@....com,
        maxime.ripard@...tlin.com, wens@...e.org, catalin.marinas@....com,
        will.deacon@....com, linux-pm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/7] dt-bindings: Add DT bindings documentation for
 Allwinner Thermal Sensor Controller

On Sat, Aug 04, 2018 at 09:03:49AM +0200, Emmanuel Vadot wrote:
> This patch adds documentation for Device-Tree bindings for the Allwinner
> Thermal Sensor Controller found on the H3, H5 and A64 SoCs
> 
> Signed-off-by: Emmanuel Vadot <manu@...ebsd.org>
> ---
>  .../bindings/thermal/allwinner-thermal.txt    | 41 +++++++++++++++++++
>  1 file changed, 41 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/thermal/allwinner-thermal.txt
> 
> diff --git a/Documentation/devicetree/bindings/thermal/allwinner-thermal.txt b/Documentation/devicetree/bindings/thermal/allwinner-thermal.txt
> new file mode 100644
> index 000000000000..5810d44cf495
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/thermal/allwinner-thermal.txt
> @@ -0,0 +1,41 @@
> +* Thermal Sensor Controller on Allwinner SoCs
> +
> +Required properties:
> +- compatible : should be "allwinner,<name>-ths"
> +   "allwinner,sun8i-h3-ths": found on H3 and H2+ SoCs
> +   "allwinner,sun50i-h5-ths": found on H5 SoC
> +   "allwinner,sun50i-a64-ths": found on H5 SoC
> +- reg : physical base address of the controller and length of memory mapped
> +	region.
> +- interrupts : The interrupt number to the cpu. The interrupt specifier format
> +	       depends on the interrupt controller.

Just need to say how many entries (and order if more than one).

> +- clocks : Must contain an entry for each entry in clock-names.
> +- clock-names : Shall be "apb" for the bus, and "ths" for
> +		the peripheral clock.
> +- resets : Must contain an entry for each entry in reset-names.
> +	   See ../reset/reset.txt for details.
> +- reset-names : Must be "apb".
> +- #thermal-sensor-cells : Depend on the SoC
> +   For H3 should be 0
> +   For H5 should be 1
> +   For A64 should be 2
> +   See ./thermal.txt for a description.
> +- nvmem-cells : Phandle to the calibration data
> +- nvmem-cell-names = Should be "ths-calib"
> +
> +Example:
> +
> +ths: thermal_sensor@...5000 {

thermal-sensor@...

> +	compatible = "allwinner,sun8i-h3-ths";
> +	reg = <0x01c25000 0x100>;
> +	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> +	clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
> +	clock-names = "apb", "ths";
> +	resets = <&ccu RST_BUS_THS>;
> +	reset-names = "apb";
> +	#thermal-sensor-cells = <0>;
> +	status = "disabled";
> +
> +	nvmem-cells = <&ths_calib>;
> +	nvmem-cell-names = "ths-calib";
> +};
> -- 
> 2.18.0
>