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Message-ID: <153434688280.37448.5200368407995060713@swboyd.mtv.corp.google.com>
Date: Wed, 15 Aug 2018 08:28:02 -0700
From: Stephen Boyd <swboyd@...omium.org>
To: Lina Iyer <ilina@...eaurora.org>, andy.gross@...aro.org,
bjorn.andersson@...aro.org
Cc: marc.zyngier@....com, rplsssn@...eaurora.org,
linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
rnayak@...eaurora.org, devicetree@...r.kernel.org,
david.brown@...aro.org, evgreen@...omium.org,
dianders@...omium.org, Lina Iyer <ilina@...eaurora.org>
Subject: Re: [PATCH] arm64: dts: msm: add PDC device bindings for sdm845
Quoting Lina Iyer (2018-08-14 10:30:58)
> Add PDC interrupt controller device bindings for SDM845.
>
> Signed-off-by: Lina Iyer <ilina@...eaurora.org>
> ---
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 24e254efb9d1..399bfbd52c5b 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -1106,6 +1106,15 @@
> };
> };
>
> + pdc: interrupt-controller@...0000 {
Please sort this by unit address within the SoC node.
> + compatible = "qcom,sdm845-pdc";
> + reg = <0xb220000 0x30000>;
> + qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&intc>;
> + interrupt-controller;
> + };
> +
> timer@...90000 {
> #address-cells = <1>;
> #size-cells = <1>;
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