Message-ID: <caea8294d20c515a33c090c4fddb15c3@codeaurora.org>
Date:   Fri, 17 Aug 2018 16:06:06 +0530
From:   dkota@...eaurora.org
To:     Mark Brown <broonie@...nel.org>
Cc:     Doug Anderson <dianders@...omium.org>,
        Stephen Boyd <swboyd@...omium.org>,
        LKML <linux-kernel@...r.kernel.org>,
        linux-spi <linux-spi@...r.kernel.org>,
        Sagar Dharia <sdharia@...eaurora.org>,
        Karthikeyan Ramasubramanian <kramasub@...eaurora.org>,
        linux-arm-msm <linux-arm-msm@...r.kernel.org>,
        "Mahadevan, Girish" <girishm@...eaurora.org>
Subject: Re: [PATCH] spi: spi-geni-qcom: Add SPI driver support for GENI based
 QUP

On 2018-08-14 20:33, Mark Brown wrote:
> On Tue, Aug 14, 2018 at 02:30:02PM +0530, dkota@...eaurora.org wrote:
>> On 2018-08-10 22:16, Mark Brown wrote:
>> > On Fri, Aug 10, 2018 at 09:59:46PM +0530, dkota@...eaurora.org wrote:
> 
>> > > delay_usecs is for inter-transfer delays within a message rather than
>> > > after the initial chip select assert (it can be used to keep chip
>> > > select
>> > > asserted for longer after the final transfer too).  Obviously this is
>> > > also something that shouldn't be configured in a driver specific
>> > > fashion.
> 
>> > Hmmm ok, so you mean don't send these as controller_data, rather add
>> > new
>> > members to the spi_device struct ?
> 
>> spi_cs_clk_delay -> Adds Delay from CS line toggle to Clock line 
>> toggle
>> spi_inter_words_delay -> Adds inter-word delay for each transfer.
> 
>> Could you please provide more information on accommodating these
>> parameters in SPI core structures like spi_device or spi_transfer? Why
>> because these are very
>> specific to Qualcomm SPI GENI controller.
> 
> I'm not sure what specific information you're looking for here - these
> things are not obviously specific to your controller, I'm even aware of
> other controllers which can do them.
> 
>> If we define them in spi core framework structures, SPI Slave driver 
>> will
>> program and expect it in the SPI transfers.
> 
> Sure.

Thanks Brown for clarifying it. As similar fields are not present in the 
spi core framework i thought these are not generic across the 
controllers.
I will add these fields in the SPI core framework structures.

Could you please clarify on below query.

>> +       mas->cur_speed_hz = spi_slv->max_speed_hz;
> 
> Why can't you use clk_get_rate() instead? Or call clk_set_rate() with
> the rate you want the master clk to run at and then divide that down
> from there?
> 
> 
>> > Not sure I follow, the intention is to run the controller clock based on
>> > the slave's max frequency.
> 
>> That's good. The problem I see is that we have to specify the max
>> frequency in the controller/bus node, and also in the child/slave
>> node.
>> It should only need to be specified in the slave node, so making the
>> cur_speed_hz equal the max_speed_hz is problematic. The current speed
>> of
>> the master should be determined by calling clk_get_rate().
> 
> We don't require that the slaves all individually set a speed since it
> gets a bit redundant, it should be enough to just use the default the
> controller provides.  A bigger problem with this is that the driver
> will
> never see a transfer which doesn't explicitly have a speed set as the
> core will ensure something is set, open coding this logic in every
> driver would obviously be tiresome.

clock_get_rate() will returns the rate which got set as per the clock
plan(which was the rounded up frequency) which can be less than or equal
to the requested frequency. For that reason using the cur_speed_hz to
store the requested frequency and skip clock configuration for the
consecutive transfers with same frequency.

--Dilip

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