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Message-ID: <DM6PR02MB52276B9FB674BC816BC28A82C13C0@DM6PR02MB5227.namprd02.prod.outlook.com>
Date: Sat, 18 Aug 2018 10:12:18 +0000
From: Manish Narani <MNARANI@...inx.com>
To: Manish Narani <MNARANI@...inx.com>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
"mark.rutland@....com" <mark.rutland@....com>,
"catalin.marinas@....com" <catalin.marinas@....com>,
"will.deacon@....com" <will.deacon@....com>,
Michal Simek <michals@...inx.com>,
"bp@...en8.de" <bp@...en8.de>,
"mchehab@...nel.org" <mchehab@...nel.org>,
"mdf@...nel.org" <mdf@...nel.org>,
Edgar Iglesias <edgari@...inx.com>,
Shubhrajyoti Datta <shubhraj@...inx.com>,
Naga Sureshkumar Relli <nagasure@...inx.com>,
Bharat Kumar Gogada <bharatku@...inx.com>,
"stefan.krsmanovic@...ios.com" <stefan.krsmanovic@...ios.com>
CC: Srinivas Goud <sgoud@...inx.com>,
Anirudha Sarangi <anirudh@...inx.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-edac@...r.kernel.org" <linux-edac@...r.kernel.org>
Subject: RE: [PATCH v4 4/4] arm64: zynqmp: Add DDRC node
Ping.
> -----Original Message-----
> From: Manish Narani [mailto:manish.narani@...inx.com]
> Sent: Saturday, August 4, 2018 2:56 PM
> To: robh+dt@...nel.org; mark.rutland@....com; catalin.marinas@....com;
> will.deacon@....com; Michal Simek <michals@...inx.com>; bp@...en8.de;
> mchehab@...nel.org; mdf@...nel.org; Edgar Iglesias <edgari@...inx.com>;
> Shubhrajyoti Datta <shubhraj@...inx.com>; Naga Sureshkumar Relli
> <nagasure@...inx.com>; Bharat Kumar Gogada <bharatku@...inx.com>;
> stefan.krsmanovic@...ios.com
> Cc: Srinivas Goud <sgoud@...inx.com>; Anirudha Sarangi
> <anirudh@...inx.com>; linux-kernel@...r.kernel.org;
> devicetree@...r.kernel.org; linux-arm-kernel@...ts.infradead.org; linux-
> edac@...r.kernel.org; Manish Narani <MNARANI@...inx.com>
> Subject: [PATCH v4 4/4] arm64: zynqmp: Add DDRC node
>
> This patch adds ddrc memory controller node in dts. The size mentioned in dts
> is 0x30000, because we need to access DDR_QOS INTR registers located at
> fd090208 from this driver.
>
> Signed-off-by: Manish Narani <manish.narani@...inx.com>
> ---
> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> index a091e6f..7d6a3cf 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> @@ -355,6 +355,13 @@
> xlnx,bus-width = <64>;
> };
>
> + mc: memory-controller@...70000 {
> + compatible = "xlnx,zynqmp-ddrc-2.40a";
> + reg = <0x0 0xfd070000 0x0 0x30000>;
> + interrupt-parent = <&gic>;
> + interrupts = <0 112 4>;
> + };
> +
> gem0: ethernet@...b0000 {
> compatible = "cdns,zynqmp-gem", "cdns,gem";
> status = "disabled";
> --
> 2.1.1
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