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Date:   Tue, 21 Aug 2018 07:59:03 -0500
From:   Rob Herring <robh@...nel.org>
To:     atish.patra@....com
Cc:     palmer@...ive.com, linux-riscv@...ts.infradead.org,
        Mark Rutland <mark.rutland@....com>,
        devicetree@...r.kernel.org, aou@...s.berkeley.edu,
        Jason Cooper <jason@...edaemon.net>,
        Marc Zyngier <marc.zyngier@....com>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        hch@...radead.org, merker@...ian.org,
        Thomas Gleixner <tglx@...utronix.de>
Subject: Re: [PATCH] dt-bindings: riscv,cpu-intc: Cleanups from a missed review

On Mon, Aug 20, 2018 at 6:10 PM Atish Patra <atish.patra@....com> wrote:
>
> On 8/20/18 4:01 PM, Palmer Dabbelt wrote:
> > I managed to miss one of Rob's code reviews on the mailing list
> > <http://lists.infradead.org/pipermail/linux-riscv/2018-August/001139.html>.
> > The patch has already been merged, so I'm submitting a fixup.
> >
> > Sorry!
> >
> > Fixes: b67bc7cb4088 ("dt-bindings: interrupt-controller: RISC-V local interrupt controller")
> > Cc: Rob Herring <robh@...nel.org>
> > Cc: Christoph Hellwig <hch@...radead.org>
> > Cc: Karsten Merker <merker@...ian.org>
> > Signed-off-by: Palmer Dabbelt <palmer@...ive.com>
> > ---
> >   .../bindings/interrupt-controller/riscv,cpu-intc.txt       | 14 +++++++++++---
> >   1 file changed, 11 insertions(+), 3 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt
> > index b0a8af51c388..265b223cd978 100644
> > --- a/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt
> > @@ -11,7 +11,7 @@ The RISC-V supervisor ISA manual specifies three interrupt sources that are
> >   attached to every HLIC: software interrupts, the timer interrupt, and external
> >   interrupts.  Software interrupts are used to send IPIs between cores.  The
> >   timer interrupt comes from an architecturally mandated real-time timer that is
> > -controller via Supervisor Binary Interface (SBI) calls and CSR reads.  External
> > +controlled via Supervisor Binary Interface (SBI) calls and CSR reads.  External
> >   interrupts connect all other device interrupts to the HLIC, which are routed
> >   via the platform-level interrupt controller (PLIC).
> >
> > @@ -25,7 +25,15 @@ in the system.
> >
> >   Required properties:
> >   - compatible : "riscv,cpu-intc"
>
> Since this is a fix up patch, we should update the compatible string
> with the sifive specific one as well. no?

I think it is fine as is if my understanding is correct. Given this is
part of the RISC-V spec(s), then using 'riscv' here for riscv,cpu-intc
is fine. It was only the PLIC which didn't have any standard
definition that I had issue with. Plus, with the SoC specific string,
I'm not too worried about what the fallback is.

However, sifive,fu540-c000-cpu-intc does need to be documented.
Putting it in the example is not documenting it.

Rob

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