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Date: Tue, 21 Aug 2018 19:18:46 +0200 From: Paul Cercueil <paul@...pouillou.net> To: Thomas Gleixner <tglx@...utronix.de>, Daniel Lezcano <daniel.lezcano@...aro.org>, Rob Herring <robh+dt@...nel.org>, Thierry Reding <thierry.reding@...il.com>, Mark Rutland <mark.rutland@....com>, Ralf Baechle <ralf@...ux-mips.org>, Paul Burton <paul.burton@...s.com>, Jonathan Corbet <corbet@....net> Cc: od@...c.me, Mathieu Malaterre <malat@...ian.org>, linux-pwm@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, linux-watchdog@...r.kernel.org, linux-mips@...ux-mips.org, linux-doc@...r.kernel.org, linux-clk@...r.kernel.org, Paul Cercueil <paul@...pouillou.net> Subject: [PATCH v7 22/24] MIPS: CI20: Reduce system timer and clocksource to 3 MHz The default clock (48 MHz) is too fast for the system timer, which fails to report time accurately. Signed-off-by: Paul Cercueil <paul@...pouillou.net> --- Notes: v5: New patch v6: Set also the rate for the clocksource channel's clock v7: No change arch/mips/boot/dts/ingenic/ci20.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts index 50cff3cbcc6d..f64d32443097 100644 --- a/arch/mips/boot/dts/ingenic/ci20.dts +++ b/arch/mips/boot/dts/ingenic/ci20.dts @@ -238,3 +238,9 @@ bias-disable; }; }; + +&tcu { + /* 3 MHz for the system timer and clocksource */ + assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>; + assigned-clock-rates = <3000000>, <3000000>; +}; -- 2.11.0
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