[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20180823133726.GA28059@infradead.org>
Date: Thu, 23 Aug 2018 06:37:26 -0700
From: Christoph Hellwig <hch@...radead.org>
To: Anup Patel <anup@...infault.org>
Cc: Christoph Hellwig <hch@...radead.org>,
Mark Rutland <mark.rutland@....com>,
Damien Le Moal <Damien.LeMoal@....com>,
"palmer@...ive.com" <palmer@...ive.com>,
"linux-kernel@...r.kernel.org List" <linux-kernel@...r.kernel.org>,
Atish Patra <atish.patra@....com>,
"linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
Thomas Gleixner <tglx@...utronix.de>
Subject: Re: [RFC PATCH 3/5] RISC-V: Add cpu_operatios structure
On Wed, Aug 22, 2018 at 08:54:51PM +0530, Anup Patel wrote:
> IMHO, rather than waiting for new CPU ON/OFF methods to come-up we
> can keep the cpu_operations ready. Also, we are not re-inventing anything
> here which we might have to discard later because cpu_operations are
> already tried and hardened for Linux ARM64.
Which is a different cpu architecture, and has shown to actually need
it. IFF we end up needing it on riscv we can still copy and paste
it from AMD64.
> I agree with you that in long-term SBI-based CPU ON/OFF will be widely
> used. Most likely we will have at-least two CPU ON/OFF methods:
> 1. Existing lottery based spinning
> 2. New SBI calls
And in this most likely case there is no need for an ops vector,
a simple if/else will be much simpler and cleaner.
Powered by blists - more mailing lists