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Message-ID: <CAKv+Gu_qz+HbU2HQ2ep0cN-9V5hA46sBNVoxvkyjDQ=ZGk8yfw@mail.gmail.com>
Date: Mon, 27 Aug 2018 17:18:26 +0200
From: Ard Biesheuvel <ard.biesheuvel@...aro.org>
To: "Theodore Y. Ts'o" <tytso@....edu>,
Ard Biesheuvel <ard.biesheuvel@...aro.org>,
linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
"open list:HARDWARE RANDOM NUMBER GENERATOR CORE"
<linux-crypto@...r.kernel.org>, Will Deacon <will.deacon@....com>,
Catalin Marinas <catalin.marinas@....com>,
Herbert Xu <herbert@...dor.apana.org.au>,
Eric Biggers <ebiggers@...gle.com>,
"Suzuki K. Poulose" <suzuki.poulose@....com>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 0/4] arm64: wire CRC32 instructions into core crc32 routines
On 27 August 2018 at 16:53, Theodore Y. Ts'o <tytso@....edu> wrote:
> On Mon, Aug 27, 2018 at 01:02:41PM +0200, Ard Biesheuvel wrote:
>> While this is not known to cause performance issues, calling a table based
>> time variant implementation with a non-negligible D-cache footprint (8 KB)
>> is wasteful in any case, and now that the crc32 instructions have been made
>> mandatory in the architecture, let's wire them up into the core crc routines.
>
> Stupid question --- are there any arm64 SOC's out there which do *not*
> have the crc32 instructions? Presumably there won't be in the future,
> because it's now mandatory --- but where there any in the past?
>
Yes, the APM Xgene for instance.
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