linux-kernel - Re: [PATCH v3 2/2] pinctrl: meson-g12a: add pinctrl driver support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CACRpkdZtzNhdY0OsT3M3YmMfHFkk5frrnf+dn=d5KfvXahRo6w@mail.gmail.com>
Date:   Wed, 29 Aug 2018 10:33:22 +0200
From:   Linus Walleij <linus.walleij@...aro.org>
To:     Yixun Lan <yixun.lan@...ogic.com>
Cc:     "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        Xingyu Chen <xingyu.chen@...ogic.com>,
        Neil Armstrong <narmstrong@...libre.com>,
        Jerome Brunet <jbrunet@...libre.com>,
        Kevin Hilman <khilman@...libre.com>,
        Carlo Caione <carlo@...one.org>,
        Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
        Rob Herring <robh@...nel.org>,
        "open list:ARM/Amlogic Meson..." <linux-amlogic@...ts.infradead.org>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3 2/2] pinctrl: meson-g12a: add pinctrl driver support

On Tue, Aug 7, 2018 at 4:07 AM Yixun Lan <yixun.lan@...ogic.com> wrote:

> Add the pinctrl driver for Meson-G12A SoC which share the similar IP as
> the previous Meson-AXG SoC, both use same pinmux ops (register layout).
> A new driver is needed here due to the differences in the pins.
>
> Starting from Meson-AXG SoC, the pinctrl controller block use 4
> continues register bits to specific the pin mux function, while comparing
> to old generation SoC which using variable length register bits for
> the pin mux definition. The new design greatly simplify the software model.
>
> For the detail example, one 32bit register can be divided into 8 parts,
> each has 4 bits whose value start from 0 - 7, each can describe one pin,
> the value 0 is always devoted to GPIO function, while 1 - 7 devoted to
> the mux pin function.
>
> Please note, the GPIOE is actually located at AO (always on) bank.
>
> Acked-by: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
> Signed-off-by: Xingyu Chen <xingyu.chen@...ogic.com>
> Signed-off-by: Yixun Lan <yixun.lan@...ogic.com>

Patch applied for v4.20.

Yours,
Linus Walleij