linux-kernel - Re: [PATCH v2] pinctrl/amd: use byte access to clear irq/wake status bits

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Message-ID: <CACRpkdb7OEC8ZFNOU915aD2e=PzOk1DasmaAq-oHCeSYVrnuTQ@mail.gmail.com>
Date:   Wed, 29 Aug 2018 13:55:24 +0200
From:   Linus Walleij <linus.walleij@...aro.org>
To:     Daniel Kurtz <djkurtz@...omium.org>
Cc:     Daniel Drake <drake@...lessm.com>,
        "S-k, Shyam-sundar" <Shyam-sundar.S-k@....com>,
        "Shah, Nehal-bakulchandra" <Nehal-bakulchandra.Shah@....com>,
        Ken Xue <Ken.Xue@....com>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2] pinctrl/amd: use byte access to clear irq/wake status bits

On Wed, Aug 22, 2018 at 6:57 PM Daniel Kurtz <djkurtz@...omium.org> wrote:

> Commit 6afb10267c1692 ("pinctrl/amd: fix masking of GPIO interrupts")
> changed to the clearing of interrupt status bits to a RMW in a critical
> section.  This works, but is a bit overkill.
>
> The relevant interrupt/wake status bits are in the Most Significant Byte
> of a 32-bit word.  These two are the only write-able bits in this byte.
>
> Therefore, it should be safe to just write these bits back as a byte
> access without any additional locking.
>
> Signed-off-by: Daniel Kurtz <djkurtz@...omium.org>

The build robot is complaining about the syntax.
Is this fixable? Maybe you already sent a new patch... I will
see when I reach the top of my inbox.

Yours,
Linus Walleij