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Date: Thu, 30 Aug 2018 14:12:55 +0100
From: Phil Edworthy <phil.edworthy@...esas.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>,
Laurent Pinchart <laurent.pinchart@...asonboard.com>
Cc: Jacopo Mondi <jacopo@...ndi.org>,
Linus Walleij <linus.walleij@...aro.org>,
Simon Horman <horms@...ge.net.au>, linux-gpio@...r.kernel.org,
linux-renesas-soc@...r.kernel.org, linux-kernel@...r.kernel.org,
Phil Edworthy <phil.edworthy@...esas.com>
Subject: [PATCH v2 3/3] ARM: dts: r9a06g032: Add pinctrl node
This provides a pinctrl driver for the Renesas R9A06G032 SoC
Based on a patch originally written by Michel Pollet at Renesas.
Signed-off-by: Phil Edworthy <phil.edworthy@...esas.com>
---
v2:
- Add "renesas,rzn1-pinctrl" compatible fallback string
- Register size corrected.
---
arch/arm/boot/dts/r9a06g032.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 1bc1f36..282ec11 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -165,6 +165,14 @@
status = "disabled";
};
+ pinctrl: pin-controller@...67000 {
+ compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
+ reg = <0x40067000 0x1000>, <0x51000000 0x480>;
+ clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
+ clock-names = "bus";
+ status = "okay";
+ };
+
gic: gic@...01000 {
compatible = "arm,cortex-a7-gic", "arm,gic-400";
interrupt-controller;
--
2.7.4
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