lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Thu, 30 Aug 2018 17:45:02 +0200 From: Philipp Rossak <embed3d@...il.com> To: lee.jones@...aro.org, robh+dt@...nel.org, mark.rutland@....com, maxime.ripard@...tlin.com, wens@...e.org, linux@...linux.org.uk, jic23@...nel.org, knaack.h@....de, lars@...afoo.de, pmeerw@...erw.net, eugen.hristev@...rochip.com, rdunlap@...radead.org, vilhelm.gray@...il.com, clabbe.montjoie@...il.com, quentin.schulz@...tlin.com, geert+renesas@...der.be, lukas@...ner.de, icenowy@...c.io, arnd@...db.de, broonie@...nel.org, arnaud.pouliquen@...com Cc: linux-iio@...r.kernel.org, devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, linux-sunxi@...glegroups.com Subject: [PATCH v3 14/30] dt-bindings: update the Allwinner GPADC device tree binding for H3 & A83T Allwinner H3 features a thermal sensor like the one in A33, but has its register re-arranged, the clock divider moved to CCU (originally the clock divider is in ADC) and added a pair of bus clock and reset. Allwinner A83T features a thermal sensor similar to the H3, the ths clock, the bus clock and the reset was removed from the CCU. The THS in A83T has a clock that is directly connected and runs with 24 MHz. Update the binding document to cover H3 and A83T. Signed-off-by: Philipp Rossak <embed3d@...il.com> --- .../devicetree/bindings/iio/adc/sun4i-gpadc.txt | 41 ++++++++++++++++++++-- 1 file changed, 38 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/sun4i-gpadc.txt b/Documentation/devicetree/bindings/iio/adc/sun4i-gpadc.txt index a7ef9dd21f04..9116ad308cf1 100644 --- a/Documentation/devicetree/bindings/iio/adc/sun4i-gpadc.txt +++ b/Documentation/devicetree/bindings/iio/adc/sun4i-gpadc.txt @@ -4,12 +4,35 @@ The Allwinner SoCs all have an ADC that can also act as a thermal sensor and sometimes as a touchscreen controller. Required properties: - - compatible: "allwinner,sun8i-a33-ths", + - compatible: must contain one of the following compatibles: + - "allwinner,sun8i-a33-ths" + - "allwinner,sun8i-h3-ths" + - "allwinner,sun8i-a83t-ths" - reg: mmio address range of the chip, - - #thermal-sensor-cells: shall be 0, + - #thermal-sensor-cells: + Please refer <devicetree/bindings/thermal/thermal.txt>, - #io-channel-cells: shall be 0, -Example: +Required properties for the following compatibles: + - "allwinner,sun8i-h3-ths" + - "allwinner,sun8i-a83t-ths" + - interrupts: the sampling interrupt of the ADC, + +Required properties for the following compatibles: + - "allwinner,sun8i-h3-ths" + - clocks: the bus clock and the input clock of the ADC, + - clock-names: should be "bus" and "mod", + - resets: the bus reset of the ADC, + +Optional properties for the following compatibles: + - "allwinner,sun8i-h3-ths" + - "allwinner,sun8i-a83t-ths" + - nvmem-cells: A phandle to the calibration data provided by a nvmem device. + - nvmem-cell-names: Should be "calibration". + +Details see: bindings/nvmem/nvmem.txt + +Example for A33: ths: ths@...5000 { compatible = "allwinner,sun8i-a33-ths"; reg = <0x01c25000 0x100>; @@ -17,6 +40,18 @@ Example: #io-channel-cells = <0>; }; +Example for H3: + ths: thermal-sensor@...5000 { + compatible = "allwinner,sun8i-h3-ths"; + reg = <0x01c25000 0x400>; + clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_THS>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + #thermal-sensor-cells = <0>; + #io-channel-cells = <0>; + }; + sun4i, sun5i and sun6i SoCs are also supported via these bindings: Required properties: -- 2.11.0
Powered by blists - more mailing lists