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Date: Thu, 30 Aug 2018 17:45:17 +0200 From: Philipp Rossak <embed3d@...il.com> To: lee.jones@...aro.org, robh+dt@...nel.org, mark.rutland@....com, maxime.ripard@...tlin.com, wens@...e.org, linux@...linux.org.uk, jic23@...nel.org, knaack.h@....de, lars@...afoo.de, pmeerw@...erw.net, eugen.hristev@...rochip.com, rdunlap@...radead.org, vilhelm.gray@...il.com, clabbe.montjoie@...il.com, quentin.schulz@...tlin.com, geert+renesas@...der.be, lukas@...ner.de, icenowy@...c.io, arnd@...db.de, broonie@...nel.org, arnaud.pouliquen@...com Cc: linux-iio@...r.kernel.org, devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, linux-sunxi@...glegroups.com Subject: [PATCH v3 29/30] ARM: dts: sun8i: a83t: add thermal zone to A83T This patch adds the thermal zones to the A83T. Sensor 0 is located besides the cpu cluster 0. Sensor 1 is located besides cluster 1 and sensor 2 is located besides in the gpu. Signed-off-by: Philipp Rossak <embed3d@...il.com> --- arch/arm/boot/dts/sun8i-a83t.dtsi | 103 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index f2f745930b08..78aa448e869f 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -50,6 +50,7 @@ #include <dt-bindings/reset/sun8i-a83t-ccu.h> #include <dt-bindings/reset/sun8i-de2.h> #include <dt-bindings/reset/sun8i-r-ccu.h> +#include <dt-bindings/thermal/thermal.h> / { interrupt-parent = <&gic>; @@ -69,6 +70,9 @@ cci-control-port = <&cci_control0>; enable-method = "allwinner,sun8i-a83t-smp"; reg = <0>; + #cooling-cells = <2>; + cooling-min-level = <0>; + cooling-max-level = <7>; }; cpu@1 { @@ -107,6 +111,9 @@ cci-control-port = <&cci_control1>; enable-method = "allwinner,sun8i-a83t-smp"; reg = <0x100>; + #cooling-cells = <2>; + cooling-min-level = <0>; + cooling-max-level = <7>; }; cpu@101 { @@ -1035,4 +1042,100 @@ #size-cells = <0>; }; }; + + thermal-zones { + cpu0_thermal: cpu0-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&ths 0>; + + trips { + cpu0_warm: cpu_warm { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu0_hot: cpu_hot { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu0_very_hot: cpu_very_hot { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu0_crit: cpu_crit { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + cpu_warm_limit_cpu { + trip = <&cpu0_warm>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT 4>; + }; + cpu_hot_limit_cpu { + trip = <&cpu0_hot>; + cooling-device = <&cpu0 5 5>; + }; + cpu_very_hot_limit_cpu { + trip = <&cpu0_very_hot>; + cooling-device = <&cpu0 7 THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu1_thermal: cpu1-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&ths 1>; + + trips { + cpu1_warm: cpu_warm { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu1_hot: cpu_hot { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu1_very_hot: cpu_very_hot { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu1_crit: cpu_crit { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + cpu_warm_limit_cpu { + trip = <&cpu1_warm>; + cooling-device = <&cpu100 THERMAL_NO_LIMIT 4>; + }; + cpu_hot_limit_cpu { + trip = <&cpu1_hot>; + cooling-device = <&cpu100 5 5>; + }; + cpu_very_hot_limit_cpu { + trip = <&cpu1_very_hot>; + cooling-device = <&cpu100 7 THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&ths 2>; + }; + }; }; -- 2.11.0
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