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Date: Thu, 30 Aug 2018 11:55:14 -0700 From: Dave Hansen <dave.hansen@...ux.intel.com> To: Andy Lutomirski <luto@...capital.net> Cc: Jann Horn <jannh@...gle.com>, yu-cheng.yu@...el.com, the arch/x86 maintainers <x86@...nel.org>, "H . Peter Anvin" <hpa@...or.com>, Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar <mingo@...hat.com>, kernel list <linux-kernel@...r.kernel.org>, linux-doc@...r.kernel.org, Linux-MM <linux-mm@...ck.org>, linux-arch <linux-arch@...r.kernel.org>, Linux API <linux-api@...r.kernel.org>, Arnd Bergmann <arnd@...db.de>, Balbir Singh <bsingharora@...il.com>, Cyrill Gorcunov <gorcunov@...il.com>, Florian Weimer <fweimer@...hat.com>, hjl.tools@...il.com, Jonathan Corbet <corbet@....net>, keescook@...omiun.org, Mike Kravetz <mike.kravetz@...cle.com>, Nadav Amit <nadav.amit@...il.com>, Oleg Nesterov <oleg@...hat.com>, Pavel Machek <pavel@....cz>, Peter Zijlstra <peterz@...radead.org>, ravi.v.shankar@...el.com, vedvyas.shanbhogue@...el.com Subject: Re: [RFC PATCH v3 12/24] x86/mm: Modify ptep_set_wrprotect and pmdp_set_wrprotect for _PAGE_DIRTY_SW On 08/30/2018 10:34 AM, Andy Lutomirski wrote: >> But, to keep B's TLB from picking up the entry, I think we can just make >> it !Present for a moment. No TLB can cache it, and I believe the same >> "don't set Dirty on a !Writable entry" logic also holds for !Present >> (modulo a weird erratum or two). > Can we get documentation? Pretty please? The accessed bit description in the SDM looks pretty good to me today: > Whenever the processor uses a paging-structure entry as part of > linear-address translation, it sets the accessed flag in that entry > (if it is not already set). If it's !Present, it can't used as part of a translation so can't be set. I think that covers the thing I was unsure about. But, Dirty is a bit, er, muddier, but mostly because it only gets set on leaf entries: > Whenever there is a write to a linear address, the processor sets the > dirty flag (if it is not already set) in the paging- structure entry > that identifies the final physical address for the linear address > (either a PTE or a paging-structure entry in which the PS flag is > 1). That little hunk will definitely need to get updated with something like: On processors enumerating support for CET, the processor will on set the dirty flag on paging structure entries in which the W flag is 1.
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